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Searched refs:PartVT (Results 1 – 16 of 16) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp152 MVT PartVT, EVT ValueVT, const Value *V,
162 unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, in getCopyFromParts() argument
168 PartVT, ValueVT, CC)) in getCopyFromParts()
172 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V, in getCopyFromParts()
181 unsigned PartBits = PartVT.getSizeInBits(); in getCopyFromParts()
195 PartVT, HalfVT, V); in getCopyFromParts()
197 RoundParts / 2, PartVT, HalfVT, V); in getCopyFromParts()
212 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts, OddParts, PartVT, in getCopyFromParts()
228 } else if (PartVT.isFloatingPoint()) { in getCopyFromParts()
230 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && in getCopyFromParts()
[all …]
H A DLegalizeVectorTypes.cpp5049 EVT PartVT = EVT::getVectorVT(*DAG.getContext(), EltVT, in WidenVecRes_EXTRACT_SUBVECTOR() local
5052 if (getTypeAction(PartVT) != TargetLowering::TypeWidenVector) { in WidenVecRes_EXTRACT_SUBVECTOR()
5057 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, PartVT, InOp, in WidenVecRes_EXTRACT_SUBVECTOR()
5060 Parts.push_back(DAG.getUNDEF(PartVT)); in WidenVecRes_EXTRACT_SUBVECTOR()
5647 EVT PartVT = EVT::getVectorVT(*DAG.getContext(), EltVT, in WidenVecRes_VECTOR_REVERSE() local
5655 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, PartVT, ReverseVal, in WidenVecRes_VECTOR_REVERSE()
5658 Parts.push_back(DAG.getUNDEF(PartVT)); in WidenVecRes_VECTOR_REVERSE()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1584 EVT PartVT = VT; in getVectorTypeBreakdown() local
1587 LK = getTypeConversion(Context, PartVT); in getVectorTypeBreakdown()
1588 PartVT = LK.second; in getVectorTypeBreakdown()
1591 if (!PartVT.isVector()) { in getVectorTypeBreakdown()
1598 PartVT.getVectorElementCount().getKnownMinValue()); in getVectorTypeBreakdown()
1599 IntermediateVT = PartVT; in getVectorTypeBreakdown()
1703 MVT PartVT = in GetReturnInfo() local
1718 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0)); in GetReturnInfo()
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h573 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
578 unsigned NumParts, MVT PartVT, EVT ValueVT,
H A DRISCVISelLowering.cpp12961 EVT PartVT = PartValue.getValueType(); in LowerCall() local
12962 if (PartVT.isScalableVector()) in LowerCall()
12964 StoredSize += PartVT.getStoreSize(); in LowerCall()
12965 StackAlign = std::max(StackAlign, getPrefTypeAlign(PartVT, DAG)); in LowerCall()
14108 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
14111 if (IsABIRegCopy && ValueVT == MVT::f16 && PartVT == MVT::f32) { in splitValueIntoRegisterParts()
14123 if (ValueVT.isScalableVector() && PartVT.isScalableVector()) { in splitValueIntoRegisterParts()
14126 EVT PartEltVT = PartVT.getVectorElementType(); in splitValueIntoRegisterParts()
14128 unsigned PartVTBitSize = PartVT.getSizeInBits().getKnownMinValue(); in splitValueIntoRegisterParts()
14147 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); in splitValueIntoRegisterParts()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h559 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
563 unsigned NumParts, MVT PartVT, EVT ValueVT,
H A DSystemZISelLowering.cpp1456 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
1459 ((NumParts == 1 && PartVT == MVT::Untyped) || in splitValueIntoRegisterParts()
1460 (NumParts == 2 && PartVT == MVT::i64))) && in splitValueIntoRegisterParts()
1472 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
1474 ((NumParts == 1 && PartVT == MVT::Untyped) || in joinRegisterPartsIntoValue()
1475 (NumParts == 2 && PartVT == MVT::i64))) && in joinRegisterPartsIntoValue()
1732 MVT PartVT = getRegisterTypeForCallingConv(Ctx, CLI.CallConv, OrigArgVT); in LowerCall() local
1734 SlotVT = EVT::getIntegerVT(Ctx, PartVT.getSizeInBits() * N); in LowerCall()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMISelLowering.h896 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
901 unsigned NumParts, MVT PartVT, EVT ValueVT,
H A DARMISelLowering.cpp4424 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
4428 PartVT == MVT::f32) { in splitValueIntoRegisterParts()
4430 unsigned PartBits = PartVT.getSizeInBits(); in splitValueIntoRegisterParts()
4433 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); in splitValueIntoRegisterParts()
4442 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
4445 PartVT == MVT::f32) { in joinRegisterPartsIntoValue()
4447 unsigned PartBits = PartVT.getSizeInBits(); in joinRegisterPartsIntoValue()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86ISelLowering.h1690 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
1695 unsigned NumParts, MVT PartVT, EVT ValueVT,
H A DX86ISelLowering.cpp2826 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
2829 if (IsABIRegCopy && ValueVT == MVT::bf16 && PartVT == MVT::f32) { in splitValueIntoRegisterParts()
2831 unsigned PartBits = PartVT.getSizeInBits(); in splitValueIntoRegisterParts()
2834 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); in splitValueIntoRegisterParts()
2843 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
2845 if (IsABIRegCopy && ValueVT == MVT::bf16 && PartVT == MVT::f32) { in joinRegisterPartsIntoValue()
2847 unsigned PartBits = PartVT.getSizeInBits(); in joinRegisterPartsIntoValue()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h1168 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
H A DPPCISelLowering.cpp18045 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
18051 if (PartVT == MVT::f64 && in splitValueIntoRegisterParts()
/openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp2478 EVT PartVT = PartValue.getValueType(); in LowerCall() local
2480 StoredSize += PartVT.getStoreSize(); in LowerCall()
2481 StackAlign = std::max(StackAlign, getPrefTypeAlign(PartVT, DAG)); in LowerCall()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DTargetLowering.h4125 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
4150 MVT PartVT, EVT ValueVT, in joinRegisterPartsIntoValue() argument
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp797 MVT PartVT = MVT::getVectorVT(VecTy.getVectorElementType(), OpsPerWord); in buildHvxVectorReg() local
799 SDValue W = buildVector32(Values.slice(i, OpsPerWord), dl, PartVT, DAG); in buildHvxVectorReg()