Searched refs:PPRRegClass (Results 1 – 6 of 6) sorted by relevance
876 } else if (AArch64::PPRRegClass.contains(Reg)) { in PrintAsmOperand()877 RegClass = &AArch64::PPRRegClass; in PrintAsmOperand()
54 if (AArch64::PPRRegClass.contains(Reg)) in regNeedsCFI()
2577 else if (AArch64::PPRRegClass.contains(RPI.Reg1)) in computeCalleeSaveRegisterPairs()3049 if (AArch64::PPRRegClass.contains(Reg) || in determineCalleeSaves()3216 AArch64::PPRRegClass.contains(CS.getReg())) { in getSVECalleeSaveSlotRange()
3539 if (AArch64::PPRRegClass.contains(DestReg) && in copyPhysReg()3540 AArch64::PPRRegClass.contains(SrcReg)) { in copyPhysReg()3847 else if (AArch64::PPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()4003 else if (AArch64::PPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
370 addRegisterClass(MVT::nxv1i1, &AArch64::PPRRegClass); in AArch64TargetLowering()371 addRegisterClass(MVT::nxv2i1, &AArch64::PPRRegClass); in AArch64TargetLowering()372 addRegisterClass(MVT::nxv4i1, &AArch64::PPRRegClass); in AArch64TargetLowering()373 addRegisterClass(MVT::nxv8i1, &AArch64::PPRRegClass); in AArch64TargetLowering()374 addRegisterClass(MVT::nxv16i1, &AArch64::PPRRegClass); in AArch64TargetLowering()6387 RC = &AArch64::PPRRegClass; in LowerFormalArguments()7181 AArch64::PPRRegClass.contains(Loc.getLocReg()); in LowerCall()10064 : std::make_pair(0U, &AArch64::PPRRegClass); in getRegForInlineAsmConstraint()
5262 auto PPRRegClass = AArch64MCRegisterClasses[AArch64::PPRRegClassID]; in validateInstruction() local5269 PPRRegClass.contains(Inst.getOperand(i).getReg())) { in validateInstruction()