Searched refs:PPR (Results 1 – 6 of 6) sorted by relevance
| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64SVEInstrInfo.td | 693 …def : Pat<(vselect (PredTy PPR:$Pg), (Ty (AArch64fma_p (PredTy (AArch64ptrue 31)), ZPR:$Zn, ZPR:$Z… 694 (!cast<Instruction>("FMLA_ZPmZZ_"#Suffix) PPR:$Pg, ZPR:$Za, ZPR:$Zn, ZPR:$Zm)>; 697 …def : Pat<(vselect (PredTy PPR:$Pg), (Ty (AArch64fma_p (PredTy (AArch64ptrue 31)), (AArch64fneg_mt… 698 (!cast<Instruction>("FMLS_ZPmZZ_"#Suffix) PPR:$Pg, ZPR:$Za, ZPR:$Zn, ZPR:$Zm)>; 1204 def : Pat<(Ty (Load (SVEDup0Undef), (nxv2i1 PPR:$gp), GPR64:$base, (nxv2i64 ZPR:$offs))), 1205 (!cast<Instruction>(Inst # _SCALED) PPR:$gp, GPR64:$base, ZPR:$offs)>; 1207 …def : Pat<(Ty (Load (SVEDup0Undef), (nxv2i1 PPR:$gp), GPR64:$base, (sext_inreg (nxv2i64 ZPR:$offs)… 1208 (!cast<Instruction>(Inst # _SXTW_SCALED) PPR:$gp, GPR64:$base, ZPR:$offs)>; 1210 …def : Pat<(Ty (Load (SVEDup0Undef), (nxv2i1 PPR:$gp), GPR64:$base, (and (nxv2i64 ZPR:$offs), (nxv2… 1211 (!cast<Instruction>(Inst # _UXTW_SCALED) PPR:$gp, GPR64:$base, ZPR:$offs)>; [all …]
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| H A D | AArch64RegisterInfo.td | 899 def PPR : PPRClass<0, 15>; 912 def PPRAsmOpAny : PPRAsmOperand<"PredicateAny", "PPR", 0>; 913 def PPRAsmOp8 : PPRAsmOperand<"PredicateB", "PPR", 8>; 914 def PPRAsmOp16 : PPRAsmOperand<"PredicateH", "PPR", 16>; 915 def PPRAsmOp32 : PPRAsmOperand<"PredicateS", "PPR", 32>; 916 def PPRAsmOp64 : PPRAsmOperand<"PredicateD", "PPR", 64>; 918 def PPRAny : PPRRegOp<"", PPRAsmOpAny, ElementSizeNone, PPR>; 919 def PPR8 : PPRRegOp<"b", PPRAsmOp8, ElementSizeB, PPR>; 920 def PPR16 : PPRRegOp<"h", PPRAsmOp16, ElementSizeH, PPR>; 921 def PPR32 : PPRRegOp<"s", PPRAsmOp32, ElementSizeS, PPR>; [all …]
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| H A D | SVEInstrFormats.td | 6106 …def : Pat<(uxtw_op (nxv4i32 ZPR:$data), (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), v… 6107 … (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>; 6108 …def : Pat<(sxtw_op (nxv4i32 ZPR:$data), (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), v… 6109 … (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>; 6126 …def : Pat<(uxtw_op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), v… 6127 … (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>; 6128 …def : Pat<(sxtw_op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), v… 6129 … (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>; 6146 …def : Pat<(uxtw_op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), v… 6147 (!cast<Instruction>(NAME # _UXTW) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>; [all …]
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| H A D | AArch64FrameLowering.cpp | 2502 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enumerator 2510 case PPR: in getScale() 2522 bool isScalable() const { return Type == PPR || Type == ZPR; } in isScalable() 2578 RPI.Type = RegPairInfo::PPR; in computeCalleeSaveRegisterPairs() 2604 case RegPairInfo::PPR: in computeCalleeSaveRegisterPairs() 2785 case RegPairInfo::PPR: in spillCalleeSavedRegisters() 2832 if (RPI.Type == RegPairInfo::ZPR || RPI.Type == RegPairInfo::PPR) in spillCalleeSavedRegisters() 2889 case RegPairInfo::PPR: in restoreCalleeSavedRegisters()
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| /openbsd-src/sys/dev/microcode/aic7xxx/ |
| H A D | aic79xx.reg | 2485 * Data Transfer Negotiation Data - PPR Options
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| H A D | aic79xx.seq | 572 * agreement. Since SPI4 only allows target reset or PPR
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