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Searched refs:OutVT (Results 1 – 12 of 12) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp41 EVT OutVT = N->getValueType(0); in ExpandRes_BITCAST() local
42 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); in ExpandRes_BITCAST()
67 TLI.hasBigEndianPartOrdering(OutVT, DL)) in ExpandRes_BITCAST()
75 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
94 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
102 if (InVT.isVector() && OutVT.isInteger()) { in ExpandRes_BITCAST()
186 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
H A DLegalizeIntegerTypes.cpp388 EVT OutVT = N->getValueType(0); in PromoteIntRes_BITCAST() local
389 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); in PromoteIntRes_BITCAST()
466 TypeSize OutSize = OutVT.getSizeInBits(); in PromoteIntRes_BITCAST()
470 EVT::getVectorVT(*DAG.getContext(), OutVT.getVectorElementType(), in PromoteIntRes_BITCAST()
471 OutVT.getVectorElementCount() * Scale); in PromoteIntRes_BITCAST()
474 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp, in PromoteIntRes_BITCAST()
483 CreateStackStoreLoad(InOp, OutVT)); in PromoteIntRes_BITCAST()
5291 EVT OutVT = V0.getValueType(); in PromoteIntRes_VECTOR_SPLICE() local
5293 return DAG.getNode(ISD::VECTOR_SPLICE, dl, OutVT, V0, V1, N->getOperand(2)); in PromoteIntRes_VECTOR_SPLICE()
5298 EVT OutVT = N->getValueType(0); in PromoteIntRes_EXTRACT_SUBVECTOR() local
[all …]
H A DLegalizeVectorTypes.cpp3039 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_UnaryOp() local
3043 Lo = DAG.getNode(N->getOpcode(), dl, { OutVT, MVT::Other }, in SplitVecOp_UnaryOp()
3045 Hi = DAG.getNode(N->getOpcode(), dl, { OutVT, MVT::Other }, in SplitVecOp_UnaryOp()
3062 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo, MaskLo, EVLLo); in SplitVecOp_UnaryOp()
3063 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi, MaskHi, EVLHi); in SplitVecOp_UnaryOp()
3065 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo); in SplitVecOp_UnaryOp()
3066 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi); in SplitVecOp_UnaryOp()
3651 EVT OutVT = N->getValueType(0); in SplitVecOp_TruncateHelper() local
3652 ElementCount NumElements = OutVT.getVectorElementCount(); in SplitVecOp_TruncateHelper()
3653 bool IsFloat = OutVT.isFloatingPoint(); in SplitVecOp_TruncateHelper()
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H A DDAGCombiner.cpp23262 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), OutSVT, NumElts / Scale); in canCombineShuffleToExtendVectorInreg() local
23264 if ((LegalTypes && !TLI.isTypeLegal(OutVT)) || in canCombineShuffleToExtendVectorInreg()
23265 (LegalOperations && !TLI.isOperationLegalOrCustom(Opcode, OutVT))) in canCombineShuffleToExtendVectorInreg()
23269 return OutVT; in canCombineShuffleToExtendVectorInreg()
23306 std::optional<EVT> OutVT = canCombineShuffleToExtendVectorInreg( in combineShuffleToAnyExtendVectorInreg() local
23308 if (!OutVT) in combineShuffleToAnyExtendVectorInreg()
23310 return DAG.getBitcast(VT, DAG.getNode(Opcode, SDLoc(SVN), *OutVT, N0)); in combineShuffleToAnyExtendVectorInreg()
23427 std::optional<EVT> OutVT = canCombineShuffleToExtendVectorInreg( in combineShuffleToZeroExtendVectorInReg() local
23430 if (OutVT) in combineShuffleToZeroExtendVectorInReg()
23431 return DAG.getBitcast(VT, DAG.getNode(Opcode, SDLoc(SVN), *OutVT, in combineShuffleToZeroExtendVectorInReg()
/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2601 EVT InVT = MVT::i16, OutVT = MVT::i8; in truncateVectorWithNARROW() local
2604 OutVT = MVT::i16; in truncateVectorWithNARROW()
2608 OutVT = EVT::getVectorVT(Ctx, OutVT, SubSizeInBits / OutVT.getSizeInBits()); in truncateVectorWithNARROW()
2618 SDValue Res = DAG.getNode(WebAssemblyISD::NARROW_U, DL, OutVT, Lo, Hi); in truncateVectorWithNARROW()
2641 EVT OutVT = N->getValueType(0); in performTruncateCombine() local
2642 if (!OutVT.isVector()) in performTruncateCombine()
2645 EVT OutSVT = OutVT.getVectorElementType(); in performTruncateCombine()
2649 (OutSVT == MVT::i8 || OutSVT == MVT::i16) && OutVT.is128BitVector())) in performTruncateCombine()
2654 OutVT.getScalarSizeInBits()); in performTruncateCombine()
2656 return truncateVectorWithNARROW(OutVT, In, DL, DAG); in performTruncateCombine()
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp4777 MVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(P.Operand * 8), in getPermuteNode() local
4779 Op = DAG.getNode(SystemZISD::PACK, DL, OutVT, Op0, Op1); in getPermuteNode()
5157 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(OutBits), in insertUnpackIfPrepared() local
5159 return DAG.getNode(SystemZISD::UNPACKL_HIGH, DL, OutVT, PackedOp); in insertUnpackIfPrepared()
5559 EVT OutVT = Op.getValueType(); in lowerSIGN_EXTEND_VECTOR_INREG() local
5561 unsigned ToBits = OutVT.getScalarSizeInBits(); in lowerSIGN_EXTEND_VECTOR_INREG()
5565 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(FromBits), in lowerSIGN_EXTEND_VECTOR_INREG() local
5568 DAG.getNode(SystemZISD::UNPACK_HIGH, SDLoc(PackedOp), OutVT, PackedOp); in lowerSIGN_EXTEND_VECTOR_INREG()
5578 EVT OutVT = Op.getValueType(); in lowerZERO_EXTEND_VECTOR_INREG() local
5581 unsigned OutNumElts = OutVT.getVectorNumElements(); in lowerZERO_EXTEND_VECTOR_INREG()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp22361 EVT InVT = MVT::i16, OutVT = MVT::i8; in truncateVectorWithPACK() local
22365 OutVT = MVT::i16; in truncateVectorWithPACK()
22371 OutVT = EVT::getVectorVT(Ctx, OutVT, 128 / OutVT.getSizeInBits()); in truncateVectorWithPACK()
22373 SDValue Res = DAG.getNode(Opcode, DL, OutVT, In, DAG.getUNDEF(InVT)); in truncateVectorWithPACK()
22384 OutVT = EVT::getVectorVT(Ctx, OutVT, SubSizeInBits / OutVT.getSizeInBits()); in truncateVectorWithPACK()
22390 SDValue Res = DAG.getNode(Opcode, DL, OutVT, Lo, Hi); in truncateVectorWithPACK()
22399 SDValue Res = DAG.getNode(Opcode, DL, OutVT, Lo, Hi); in truncateVectorWithPACK()
22405 int Scale = 64 / OutVT.getScalarSizeInBits(); in truncateVectorWithPACK()
22407 Res = DAG.getVectorShuffle(OutVT, DL, Res, Res, Mask); in truncateVectorWithPACK()
51479 EVT OutVT = N->getValueType(0); in combineVectorTruncationWithPACKUS() local
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H A DX86InstrSSE.td3778 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
3789 (OutVT (OpNode (ArgVT RC:$src1), RC:$src2)))]>,
3798 (OutVT (OpNode (ArgVT RC:$src1),
3803 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
3814 (OutVT (OpNode (ArgVT RC:$src1), RC:$src2)))]>,
3823 (OutVT (OpNode (ArgVT RC:$src1),
H A DX86InstrAVX512.td349 multiclass AVX512_maskable_3src_cast<bits<8> O, Format F, X86VectorVTInfo OutVT,
354 AVX512_maskable_common<O, F, OutVT, Outs,
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DSVEInstrFormats.td2566 ValueType OutVT, ValueType InVT,
2569 …def : SVE_4_Op_Imm_Pat<OutVT, op, OutVT, InVT, InVT, i32, VectorIndexH32b_timm, !cast<Instruction>…
2600 multiclass sve2_fp_mla_long<bits<3> opc, string asm, ValueType OutVT,
2603 def : SVE_3_Op_Pat<OutVT, op, OutVT, InVT, InVT, !cast<Instruction>(NAME)>;
H A DAArch64ISelLowering.cpp17900 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); in getPTest() local
17901 SDValue TVal = DAG.getConstant(1, DL, OutVT); in getPTest()
17902 SDValue FVal = DAG.getConstant(0, DL, OutVT); in getPTest()
17922 SDValue Res = DAG.getNode(AArch64ISD::CSEL, DL, OutVT, FVal, TVal, CC, Test); in getPTest()
21009 SDValue OutVT = DAG.getValueType(RetVT); in performGatherLoadCombine() local
21011 OutVT = DAG.getValueType(HwRetVt); in performGatherLoadCombine()
21016 Base, Offset, OutVT}; in performGatherLoadCombine()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp8516 EVT OutVT = Op.getValueType(); in LowerINT_TO_FP() local
8517 if (OutVT.isVector() && OutVT.isFloatingPoint() && in LowerINT_TO_FP()