| /openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/ |
| H A D | SparcInstrVIS.td | 18 class VISInst<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs> 21 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>; 24 class VISInstID<bits<9> opfval, string OpcStr> 27 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>; 36 class VISInst1<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs> 39 !strconcat(OpcStr, " $rs1, $rd"), []>; 43 class VISInst2<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs> 46 !strconcat(OpcStr, " $rs2, $rd"), []>; 50 class VISInstD<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs> 53 !strconcat(OpcStr, " $rd"), []>;
|
| H A D | SparcInstr64Bit.td | 359 multiclass BranchOnReg<bits<3> cond, string OpcStr> { 361 !strconcat(OpcStr, " $rs1, $imm16"), []>; 363 !strconcat(OpcStr, ",a $rs1, $imm16"), []>; 365 !strconcat(OpcStr, ",pn $rs1, $imm16"), []>; 367 !strconcat(OpcStr, ",a,pn $rs1, $imm16"), []>; 370 multiclass bpr_alias<string OpcStr, Instruction NAPT, Instruction APT> { 371 def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"), 373 def : InstAlias<!strconcat(OpcStr, ",a,pt $rs1, $imm16"),
|
| H A D | SparcInstrInfo.td | 376 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode, 381 !strconcat(OpcStr, " $rs1, $rs2, $rd"), 386 !strconcat(OpcStr, " $rs1, $simm13, $rd"), 393 multiclass F3_12np<string OpcStr, bits<6> Op3Val, InstrItinClass itin = IIC_iu_instr> { 396 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [], 400 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [], 405 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, 409 !strconcat(OpcStr, " [$addr], $rd"), 414 !strconcat(OpcStr, " [$addr], $rd"), 421 class LoadASI<string OpcStr, bits<6> Op3Val, RegisterClass RC> : [all …]
|
| H A D | SparcInstrFormats.td | 226 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode, 230 !strconcat(OpcStr, " $rs1, $rs2, $rd"), 234 !strconcat(OpcStr, " $rs1, $shcnt, $rd"),
|
| /openbsd-src/gnu/llvm/llvm/lib/Target/XCore/ |
| H A D | XCoreInstrInfo.td | 208 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> { 210 !strconcat(OpcStr, " $dst, $b, $c"), 213 !strconcat(OpcStr, " $dst, $b, $c"), 217 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> { 219 !strconcat(OpcStr, " $dst, $b, $c"), []>; 221 !strconcat(OpcStr, " $dst, $b, $c"), []>; 224 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr, 227 !strconcat(OpcStr, " $dst, $b, $c"), 230 !strconcat(OpcStr, " $dst, $b, $c"), 234 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> : [all …]
|
| /openbsd-src/gnu/llvm/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXInstrInfo.td | 204 // The instructions are named "<OpcStr><Width>" (e.g. "add.s64"). 205 multiclass I3<string OpcStr, SDNode OpNode> { 208 !strconcat(OpcStr, "64 \t$dst, $a, $b;"), 212 !strconcat(OpcStr, "64 \t$dst, $a, $b;"), 216 !strconcat(OpcStr, "32 \t$dst, $a, $b;"), 220 !strconcat(OpcStr, "32 \t$dst, $a, $b;"), 224 !strconcat(OpcStr, "16 \t$dst, $a, $b;"), 228 !strconcat(OpcStr, "16 \t$dst, $a, $b;"), 233 // named "<OpcStr>.s32" (e.g. "addc.cc.s32"). 234 multiclass ADD_SUB_INT_CARRY<string OpcStr, SDNode OpNode> { [all …]
|
| H A D | NVPTXIntrinsics.td | 549 // We need a full string for OpcStr here because we need to deal with case like 551 class F_MATH_1<string OpcStr, NVPTXRegClass target_regclass, 554 OpcStr, 558 // We need a full string for OpcStr here because we need to deal with the case 560 class F_MATH_2<string OpcStr, NVPTXRegClass t_regclass, 565 OpcStr, 569 class F_MATH_3<string OpcStr, NVPTXRegClass t_regclass, 574 OpcStr, 1432 string SpaceStr, string TypeStr, string OpcStr, PatFrag IntOp, 1435 !strconcat("atom", SpaceStr, OpcStr, TypeStr, " \t$dst, [$addr], $b;"), [all …]
|
| /openbsd-src/gnu/llvm/llvm/lib/Target/BPF/ |
| H A D | BPFInstrInfo.td | 694 string OpcStr, PatFrag OpNode> 698 "$dst = atomic_fetch_"#OpcStr#"(("#OpcodeStr#" *)($addr), $val)", 712 string OpcStr, PatFrag OpNode> 716 "$dst = atomic_fetch_"#OpcStr#"(("#OpcodeStr#" *)($addr), $val)",
|
| /openbsd-src/gnu/llvm/llvm/docs/ |
| H A D | WritingAnLLVMBackend.rst | 806 multiclass F3_12 <string OpcStr, bits<6> Op3Val, SDNode OpNode> { 809 !strconcat(OpcStr, " $rs1, $rs2, $rd"), 813 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
|
| /openbsd-src/gnu/llvm/clang/lib/Sema/ |
| H A D | SemaOverload.cpp | 14161 StringRef OpcStr = BinaryOperator::getOpcodeStr(Opc); in CreateOverloadedBinOp() local 14190 CandidateSet.NoteCandidates(*this, Args, Cands, OpcStr, OpLoc); in CreateOverloadedBinOp()
|