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Searched refs:OpNode (Results 1 – 25 of 41) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/VE/
H A DVVPInstrPatternsVec.td181 multiclass Binary_rv<SDPatternOperator OpNode,
186 (OpNode
202 def : Pat<(OpNode
209 def : Pat<(OpNode
217 multiclass Binary_vr<SDPatternOperator OpNode,
222 (OpNode
238 def : Pat<(OpNode
245 def : Pat<(OpNode
253 multiclass Binary_vv<SDPatternOperator OpNode,
258 (OpNode
[all …]
H A DVEInstrInfo.td545 SDPatternOperator OpNode = null_frag,
550 [(set Tyo:$sx, (OpNode Tyi:$sy, Tyi:$sz))]>;
551 // VE calculates (OpNode $sy, $sz), but llvm requires to have immediate
556 [(set Tyo:$sx, (OpNode Tyi:$sz, (Tyi immOp:$sy)))]>;
560 [(set Tyo:$sx, (OpNode Tyi:$sy, (Tyi mOp:$sz)))]>;
564 [(set Tyo:$sx, (OpNode (Tyi immOp:$sy), (Tyi mOp:$sz)))]> {
577 SDPatternOperator OpNode = null_frag,
581 [(set Tyo:$sx, (OpNode Tyi:$sy, Tyi:$sz))]>;
585 [(set Tyo:$sx, (OpNode (Tyi immOp:$sy), Tyi:$sz))]>;
589 [(set Tyo:$sx, (OpNode Tyi:$sy, (Tyi mOp:$sz)))]>;
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.h85 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
87 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
89 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
91 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
93 bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
95 bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
H A DNVPTXInstrInfo.td205 multiclass I3<string OpcStr, SDNode OpNode> {
209 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, Int64Regs:$b))]>;
213 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
217 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
221 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
225 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, Int16Regs:$b))]>;
229 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, (imm):$b))]>;
234 multiclass ADD_SUB_INT_CARRY<string OpcStr, SDNode OpNode> {
239 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
243 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td2235 SDPatternOperator OpNode>
2238 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64sp:$Rm))]>,
2306 SDNode OpNode>
2308 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
2311 SDNode OpNode>
2313 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
2319 SDNode OpNode, SDNode OpNode_setflags> {
2320 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
2324 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
2343 string asm, SDPatternOperator OpNode,
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstrAVX512.td1355 X86VectorVTInfo _, SDPatternOperator OpNode,
1362 (_.VT (OpNode SrcRC:$src)), /*IsCommutable*/0,
1368 X86VectorVTInfo _, SDPatternOperator OpNode,
1378 def : Pat <(_.VT (OpNode SrcRC:$src)),
1383 def : Pat <(vselect _.KRCWM:$mask, (_.VT (OpNode SrcRC:$src)), _.RC:$src0),
1387 def : Pat <(vselect _.KRCWM:$mask, (_.VT (OpNode SrcRC:$src)), _.ImmAllZerosV),
1393 AVX512VLVectorVTInfo _, SDPatternOperator OpNode,
1397 OpNode, SrcRC, Subreg>, EVEX_V512;
1400 _.info256, OpNode, SrcRC, Subreg>, EVEX_V256;
1402 _.info128, OpNode, SrcRC, Subreg>, EVEX_V128;
[all …]
H A DX86InstrFMA.td179 SDPatternOperator OpNode,
185 [(set RC:$dst, (OpNode RC:$src2, RC:$src1, RC:$src3))]>,
194 (OpNode RC:$src2, RC:$src1, (load addr:$src3)))]>,
200 SDPatternOperator OpNode, X86FoldableSchedWrite sched> {
214 (OpNode RC:$src2, (load addr:$src3), RC:$src1))]>,
220 SDPatternOperator OpNode, X86FoldableSchedWrite sched> {
236 (OpNode (load addr:$src3), RC:$src1, RC:$src2))]>,
244 SDPatternOperator OpNode, RegisterClass RC,
247 x86memop, RC, OpNode, sched>;
249 x86memop, RC, OpNode, sched>;
[all …]
H A DX86InstrFPStack.td190 multiclass FPBinary_rr<SDPatternOperator OpNode> {
194 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
196 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
198 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
203 multiclass FPBinary<SDPatternOperator OpNode, Format fp, string asmstring,
210 (OpNode RFP32:$src1, (loadf32 addr:$src2))),
212 (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>;
217 (OpNode RFP64:$src1, (loadf64 addr:$src2))),
219 (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>;
224 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))),
[all …]
H A DX86InstrXOP.td94 multiclass xop3op<bits<8> opc, string OpcodeStr, SDNode OpNode,
100 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>,
106 (vt128 (OpNode (vt128 VR128:$src1),
113 (vt128 (OpNode (vt128 (load addr:$src1)),
140 multiclass xop3opimm<bits<8> opc, string OpcodeStr, SDNode OpNode,
146 (vt128 (OpNode (vt128 VR128:$src1), timm:$src2)))]>,
152 (vt128 (OpNode (vt128 (load addr:$src1)), timm:$src2)))]>,
244 multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128,
253 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
261 (vt128 (OpNode (vt128 VR128:$src1),
[all …]
H A DX86InstrSSE.td20 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], d>,
37 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], d>,
44 SDPatternOperator OpNode, RegisterClass RC,
53 [(set RC:$dst, (VT (OpNode RC:$src1, RC:$src2)))], d>,
60 [(set RC:$dst, (VT (OpNode RC:$src1, (mem_frags addr:$src2))))], d>,
66 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
76 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>,
83 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
194 multiclass sse12_move_rr<SDNode OpNode, ValueType vt, string base_opc,
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsDSPInstrInfo.td266 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
272 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
277 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
283 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
288 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
294 list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
299 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
305 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
310 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
316 list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, timmZExt5:$sa))];
[all …]
H A DMipsInstrFPU.td112 SDPatternOperator OpNode= null_frag> :
115 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
121 SDPatternOperator OpNode = null_frag> {
122 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32;
123 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
129 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
131 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
137 SDPatternOperator OpNode = null_frag> :
140 [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>,
146 SDPatternOperator OpNode= null_frag> {
[all …]
H A DMipsMSAInstrInfo.td1118 class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1125 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1129 class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1136 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1140 class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1147 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1151 class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1158 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1162 class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1169 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
[all …]
H A DMicroMipsInstrFPU.td14 SDPatternOperator OpNode = null_frag> {
15 def _D32_MM : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
20 def _D64_MM : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
111 SDPatternOperator OpNode = null_frag> {
112 def _D32_MM : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
116 def _D64_MM : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
H A DMicroMipsDSPInstrInfo.td179 class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
185 list<dag> Pattern = [(set ROD:$rt, (OpNode ROS:$rs))];
215 class SHLL_R2_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
221 list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, ImmPat:$sa))];
252 class SHLLV_R3_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
257 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))];
325 class MFHI_MM_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
330 list<dag> Pattern = [(set GPR32Opnd:$rs, (OpNode RO:$ac))];
H A DMipsInstrInfo.td1319 SDPatternOperator OpNode = null_frag>:
1322 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
1332 SDPatternOperator OpNode = null_frag> :
1335 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
1361 SDPatternOperator OpNode = null_frag,
1365 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
1370 SDPatternOperator OpNode = null_frag>:
1373 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
1386 SDPatternOperator OpNode = null_frag,
1390 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
[all …]
H A DMipsCondMov.td36 SDPatternOperator OpNode = null_frag> :
39 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
46 SDPatternOperator OpNode = null_frag> :
49 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
H A DMips16InstrInfo.td1312 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1313 Mips16Pat<(OpNode CPU16Regs:$r),
1319 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1320 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1332 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1333 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1342 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1343 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1350 class LoadM16_pat<PatFrag OpNode, Instruction I, ComplexPattern Addr> :
1351 Mips16Pat<(OpNode Addr:$addr), (I Addr:$addr)>;
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td265 multiclass ALU<BPFArithOp Opc, string OpcodeStr, SDNode OpNode> {
270 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;
275 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]>;
280 [(set GPR32:$dst, (OpNode i32:$src2, i32:$src))]>;
285 [(set GPR32:$dst, (OpNode GPR32:$src2, i32immSExt32:$imm))]>;
413 class STOREi64<BPFWidthModifer Opc, string OpcodeStr, PatFrag OpNode>
414 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
439 class LOADi64<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
440 : LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
623 class XADD<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td287 multiclass ALUarith<bits<3> subOp, string AsmStr, SDNode OpNode,
295 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
298 multiclass ALUlogic<bits<3> subOp, string AsmStr, SDNode OpNode,
301 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
302 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
308 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
479 class LoadRR<string OpcString, PatFrag OpNode, ValueType Ty>
482 [(set (Ty GPR:$Rd), (OpNode ADDRrr:$src))]>,
495 class LoadRI<string OpcString, PatFrag OpNode, ValueType Ty>
498 [(set (Ty GPR:$Rd), (OpNode ADDRri:$src))]>,
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMInstrNEON.td2509 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2512 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2515 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2518 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2574 ValueType TyD, ValueType TyQ, SDNode OpNode>
2577 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2592 ValueType TyQ, ValueType TyD, SDNode OpNode>
2595 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2621 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2625 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td208 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
211 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
214 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
225 SDNode OpNode> {
228 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
231 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
234 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
237 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
246 SDNode OpNode> {
249 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td139 class PatFpr<SDPatternOperator OpNode, LAInst Inst, RegisterClass RegTy>
140 : Pat<(OpNode RegTy:$fj), (Inst $fj)>;
141 class PatFprFpr<SDPatternOperator OpNode, LAInst Inst, RegisterClass RegTy>
142 : Pat<(OpNode RegTy:$fj, RegTy:$fk), (Inst $fj, $fk)>;
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZk.td136 class PatGprGprByteSelect<SDPatternOperator OpNode, RVInst Inst>
137 : Pat<(OpNode GPR:$rs1, GPR:$rs2, i8:$imm),
/openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcInstrFormats.td226 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
231 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))],
235 [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))],

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