| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMHazardRecognizer.cpp | 192 int64_t Offset0 = 0; in getHazardType() local
210 Ptr0 = GetPointerBaseWithConstantOffset(BaseVal0, Offset0, DL, true); in getHazardType()
213 return CheckOffsets(Offset0, Offset1); in getHazardType()
222 Offset0 = MF.getFrameInfo().getObjectOffset(FS0->getFrameIndex()); in getHazardType()
224 return CheckOffsets(Offset0, Offset1); in getHazardType()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.h | 158 bool isDSOffset2Legal(SDValue Base, unsigned Offset0, unsigned Offset1,
161 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
163 bool SelectDS128Bit8ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
165 bool SelectDSReadWrite2(SDValue Ptr, SDValue &Base, SDValue &Offset0,
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| H A D | AMDGPUISelDAGToDAG.cpp | 1127 bool AMDGPUDAGToDAGISel::isDSOffset2Legal(SDValue Base, unsigned Offset0, in isDSOffset2Legal() argument
1130 if (Offset0 % Size != 0 || Offset1 % Size != 0) in isDSOffset2Legal()
1132 if (!isUInt<8>(Offset0 / Size) || !isUInt<8>(Offset1 / Size)) in isDSOffset2Legal()
1146 SDValue &Offset0, in SelectDS64Bit4ByteAligned() argument
1148 return SelectDSReadWrite2(Addr, Base, Offset0, Offset1, 4); in SelectDS64Bit4ByteAligned()
1152 SDValue &Offset0, in SelectDS128Bit8ByteAligned() argument
1154 return SelectDSReadWrite2(Addr, Base, Offset0, Offset1, 8); in SelectDS128Bit8ByteAligned()
1158 SDValue &Offset0, SDValue &Offset1, in SelectDSReadWrite2() argument
1172 Offset0 = CurDAG->getTargetConstant(OffsetValue0 / Size, DL, MVT::i8); in SelectDSReadWrite2()
1208 Offset0 = CurDAG->getTargetConstant(OffsetValue0 / Size, DL, MVT::i8); in SelectDSReadWrite2()
[all …]
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| H A D | AMDGPUInstructionSelector.h | 237 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
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| H A D | SIInstrInfo.cpp | 173 int64_t &Offset0, in areLoadsFromSameBasePtr() argument
209 Offset0 = cast<ConstantSDNode>(Load0->getOperand(Offset0Idx))->getZExtValue(); in areLoadsFromSameBasePtr()
241 Offset0 = Load0Offset->getZExtValue(); in areLoadsFromSameBasePtr()
274 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue(); in areLoadsFromSameBasePtr()
332 unsigned Offset0 = Offset0Op->getImm(); in getMemOperandsWithOffsetWidth() local
334 if (Offset0 + 1 != Offset1) in getMemOperandsWithOffsetWidth()
353 Offset = EltSize * Offset0; in getMemOperandsWithOffsetWidth()
525 int64_t Offset0, int64_t Offset1, in shouldScheduleLoadsNear() argument
527 assert(Offset1 > Offset0 && in shouldScheduleLoadsNear()
533 return (NumLoads <= 16 && (Offset1 - Offset0) < 64); in shouldScheduleLoadsNear()
[all …]
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| H A D | SIInstrInfo.h | 191 bool areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, int64_t &Offset0,
204 bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
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| H A D | AMDGPUInstructionSelector.cpp | 1545 unsigned Offset0 = OrderedCountIndex << 2; in selectDSOrderedIntrinsic() local
1554 unsigned Offset = Offset0 | (Offset1 << 8); in selectDSOrderedIntrinsic()
4276 bool AMDGPUInstructionSelector::isDSOffset2Legal(Register Base, int64_t Offset0, in isDSOffset2Legal() argument
4279 if (Offset0 % Size != 0 || Offset1 % Size != 0) in isDSOffset2Legal()
4281 if (!isUInt<8>(Offset0 / Size) || !isUInt<8>(Offset1 / Size)) in isDSOffset2Legal()
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| H A D | SIInstrInfo.td | 1234 def offset0 : NamedIntOperand<i8, "offset0", "Offset0">;
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| H A D | SIISelLowering.cpp | 7299 unsigned Offset0 = OrderedCountIndex << 2; in LowerINTRINSIC_W_CHAIN() local
7308 unsigned Offset = Offset0 | (Offset1 << 8); in LowerINTRINSIC_W_CHAIN()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 397 int64_t Offset0; in apply() local
399 MachineOperand *BaseOp0 = HII.getBaseAndOffset(L0, Offset0, Size0); in apply()
418 if (((Offset0 ^ Offset1) & 0x18) != 0) in apply()
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| H A D | HexagonISelLoweringHVX.cpp | 2196 SDValue Offset0 = DAG.getTargetConstant(0, dl, ty(Base)); in LowerHvxMaskedOp() local
2200 {Mask, Base, Offset0, Value, Chain}, DAG); in LowerHvxMaskedOp()
2227 {MaskU.first, Base, Offset0, ValueU.first, Chain}, DAG); in LowerHvxMaskedOp()
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| /openbsd-src/gnu/llvm/llvm/lib/Analysis/ |
| H A D | ConstantFolding.cpp | 1304 APInt Offset0(IndexWidth, 0); in ConstantFoldCompareInstOperands() local
1306 Ops0->stripAndAccumulateInBoundsConstantOffsets(DL, Offset0); in ConstantFoldCompareInstOperands()
1313 ConstantInt::get(CE0->getContext(), Offset0), in ConstantFoldCompareInstOperands()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 17043 const APInt &Offset0 = CN->getAPIntValue(); in CombineToPreIndexedLoadStore() local
17052 APInt CNV = Offset0; in CombineToPreIndexedLoadStore()
19231 int64_t Offset0 = LoadNodes[0].OffsetFromBase; in tryStoreMergeOfLoads() local
19234 if (Offset0 - Offset1 == ElementSizeBytes && in tryStoreMergeOfLoads()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 8547 bool Offset0 = false, Offset1 = false; in getFauxShuffleMask() local
8559 Offset0 = true; in getFauxShuffleMask()
8584 if (Offset0 || Offset1) { in getFauxShuffleMask()
8586 if ((Offset0 && isInRange(M, 0, NumElts)) || in getFauxShuffleMask()
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