| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 217 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
225 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
233 unsigned NumVecs, const uint16_t *DOpcodes,
290 void SelectMVE_VLD(SDNode *N, unsigned NumVecs,
311 unsigned NumVecs, const uint16_t *DOpcodes,
349 SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
1940 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1941 unsigned NumRegs = NumVecs; in GetVLDSTAlign()
1942 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
2105 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) { in isPerfectIncrement() argument
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| H A D | ARMISelLowering.cpp | 15672 unsigned NumVecs = 0; in TryCombineBaseUpdate() local
15680 NumVecs = 1; in TryCombineBaseUpdate()
15684 NumVecs = 2; in TryCombineBaseUpdate()
15688 NumVecs = 3; in TryCombineBaseUpdate()
15692 NumVecs = 4; in TryCombineBaseUpdate()
15696 NumVecs = 2; in TryCombineBaseUpdate()
15701 NumVecs = 3; in TryCombineBaseUpdate()
15706 NumVecs = 4; in TryCombineBaseUpdate()
15711 NumVecs = 2; in TryCombineBaseUpdate()
15715 NumVecs = 3; in TryCombineBaseUpdate()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 343 void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
350 void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
352 void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
354 void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
355 void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
356 void SelectPredicatedLoad(SDNode *N, unsigned NumVecs, unsigned Scale,
360 void SelectCVTIntrinsic(SDNode *N, unsigned NumVecs, unsigned Opcode);
378 void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
379 void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
380 void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
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| H A D | AArch64ISelLowering.cpp | 13404 template <unsigned NumVecs>
13414 for (unsigned I = 0; I < NumVecs; ++I) in setInfoSVEStN()
13420 EC * NumVecs); in setInfoSVEStN()
19596 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
19601 NumVecs = 2; break; in performNEONPostLDSTCombine()
19603 NumVecs = 3; break; in performNEONPostLDSTCombine()
19605 NumVecs = 4; break; in performNEONPostLDSTCombine()
19607 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
19609 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
19611 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
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| H A D | AArch64TargetTransformInfo.cpp | 3148 unsigned NumVecs = (TpNumElts + LTNumElts - 1) / LTNumElts; in getShuffleCost() local
3152 for (unsigned N = 0; N < NumVecs; N++) { in getShuffleCost()
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| /openbsd-src/gnu/llvm/llvm/lib/Analysis/ |
| H A D | VectorUtils.cpp | 967 unsigned NumVecs) { in createInterleaveMask() argument
970 for (unsigned j = 0; j < NumVecs; j++) in createInterleaveMask()
1042 unsigned NumVecs = Vecs.size(); in concatenateVectors() local
1043 assert(NumVecs > 1 && "Should be at least two vectors"); in concatenateVectors()
1049 for (unsigned i = 0; i < NumVecs - 1; i += 2) { in concatenateVectors()
1051 assert((V0->getType() == V1->getType() || i == NumVecs - 2) && in concatenateVectors()
1058 if (NumVecs % 2 != 0) in concatenateVectors()
1059 TmpList.push_back(ResList[NumVecs - 1]); in concatenateVectors()
1062 NumVecs = ResList.size(); in concatenateVectors()
1063 } while (NumVecs > 1); in concatenateVectors()
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| /openbsd-src/gnu/llvm/llvm/include/llvm/Analysis/ |
| H A D | VectorUtils.h | 537 llvm::SmallVector<int, 16> createInterleaveMask(unsigned VF, unsigned NumVecs);
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 187 bool selectVectorLoadIntrinsic(unsigned Opc, unsigned NumVecs,
5613 unsigned NumVecs, in selectVectorLoadIntrinsic() argument
5617 assert(NumVecs > 1 && NumVecs < 5 && "Only support 2, 3, or 4 vectors"); in selectVectorLoadIntrinsic()
5630 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in selectVectorLoadIntrinsic()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 10640 int NumVecs = 2; in LowerINTRINSIC_WO_CHAIN() local
10643 NumVecs = 4; in LowerINTRINSIC_WO_CHAIN()
10647 for (int VecNo = 0; VecNo < NumVecs; VecNo++) { in LowerINTRINSIC_WO_CHAIN()
10650 DAG.getConstant(Subtarget.isLittleEndian() ? NumVecs - 1 - VecNo in LowerINTRINSIC_WO_CHAIN()
11061 unsigned NumVecs = VT.getSizeInBits() / 128; in LowerVectorLoad() local
11062 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in LowerVectorLoad()
11107 unsigned NumVecs = 2; in LowerVectorStore() local
11118 NumVecs = 4; in LowerVectorStore()
11120 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in LowerVectorStore()
11121 unsigned VecNum = Subtarget.isLittleEndian() ? NumVecs - 1 - Idx : Idx; in LowerVectorStore()
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| /openbsd-src/gnu/llvm/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 16489 unsigned NumVecs = 2; in EmitPPCBuiltinExpr() local
16492 NumVecs = 4; in EmitPPCBuiltinExpr()
16501 for (unsigned i=0; i<NumVecs; i++) { in EmitPPCBuiltinExpr()
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