Searched refs:NotOpc (Results 1 – 4 of 4) sorted by relevance
| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 110 unsigned NotOpc; member
132 NotOpc = AMDGPU::S_NOT_B32; in SGPRSpillBuilder()
136 NotOpc = AMDGPU::S_NOT_B64; in SGPRSpillBuilder()
228 auto I = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg); in prepare()
263 auto I = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg); in restore()
302 auto Not0 = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg); in readWriteTmpVGPR()
305 auto Not1 = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg); in readWriteTmpVGPR()
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| H A D | SIInstrInfo.cpp | 2036 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64; in expandPostRAPseudo() local
2042 auto FirstNot = BuildMI(MBB, MI, DL, get(NotOpc), Exec).addReg(Exec); in expandPostRAPseudo()
2046 BuildMI(MBB, MI, DL, get(NotOpc), Exec) in expandPostRAPseudo()
2052 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64; in expandPostRAPseudo() local
2058 auto FirstNot = BuildMI(MBB, MI, DL, get(NotOpc), Exec).addReg(Exec); in expandPostRAPseudo()
2064 BuildMI(MBB, MI, DL, get(NotOpc), Exec) in expandPostRAPseudo()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3959 unsigned NotOpc = Pred == ICmpInst::ICMP_NE ? AArch64::NOTv8i8 : 0; in selectVectorICmp() local
3961 NotOpc = NotOpc ? AArch64::NOTv16i8 : 0; in selectVectorICmp()
3970 if (NotOpc) { in selectVectorICmp()
3971 Cmp = MIB.buildInstr(NotOpc, {DstReg}, {Cmp}); in selectVectorICmp()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 3468 unsigned NotOpc; in tryShiftAmountMod() local
3472 NotOpc = AArch64::ORNWrr; in tryShiftAmountMod()
3476 NotOpc = AArch64::ORNXrr; in tryShiftAmountMod()
3482 CurDAG->getMachineNode(NotOpc, DL, SubVT, Zero, Add1); in tryShiftAmountMod()
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