Home
last modified time | relevance | path

Searched refs:NewVT (Results 1 – 25 of 25) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp218 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); in ExpandRes_EXTRACT_VECTOR_ELT() local
231 EVT::getVectorVT(*DAG.getContext(), NewVT, OldEltCount * 2), OldVec); in ExpandRes_EXTRACT_VECTOR_ELT()
237 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
241 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
373 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); in ExpandOp_BUILD_VECTOR() local
393 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NewElts.size()); in ExpandOp_BUILD_VECTOR()
H A DLegalizeVectorTypes.cpp312 EVT NewVT = N->getValueType(0).getVectorElementType(); in ScalarizeVecRes_BITCAST() local
314 NewVT, Op); in ScalarizeVecRes_BITCAST()
2362 EVT NewVT = Inputs[0].getValueType(); in SplitVecRes_VECTOR_SHUFFLE() local
2363 unsigned NewElts = NewVT.getVectorNumElements(); in SplitVecRes_VECTOR_SHUFFLE()
2371 auto &&BuildVector = [NewElts, &DAG = DAG, NewVT, &DL](SDValue &Input1, in SplitVecRes_VECTOR_SHUFFLE()
2377 EVT EltVT = NewVT.getVectorElementType(); in SplitVecRes_VECTOR_SHUFFLE()
2391 return DAG.getBuildVector(NewVT, DL, Ops); in SplitVecRes_VECTOR_SHUFFLE()
2399 auto &&TryPeekThroughShufflesInputs = [&Inputs, &NewVT, this, NewElts, in SplitVecRes_VECTOR_SHUFFLE()
2518 if (Shuffle->getOperand(0).getValueType() != NewVT) in SplitVecRes_VECTOR_SHUFFLE()
2674 [&Output, &DAG = DAG, NewVT]() { Output = DAG.getUNDEF(NewVT); }, in SplitVecRes_VECTOR_SHUFFLE()
[all …]
H A DDAGCombiner.cpp4763 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); in visitMULHS() local
4764 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHS()
4765 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); in visitMULHS()
4766 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); in visitMULHS()
4767 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); in visitMULHS()
4768 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHS()
4833 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); in visitMULHU() local
4834 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHU()
4835 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); in visitMULHU()
4836 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); in visitMULHU()
[all …]
H A DTargetLowering.cpp235 EVT NewVT = VT; in findOptimalMemOpLowering() local
240 NewVT = (VT.getSizeInBits() > 64) ? MVT::i64 : MVT::i32; in findOptimalMemOpLowering()
241 if (isOperationLegalOrCustom(ISD::STORE, NewVT) && in findOptimalMemOpLowering()
242 isSafeMemOpType(NewVT.getSimpleVT())) in findOptimalMemOpLowering()
244 else if (NewVT == MVT::i64 && in findOptimalMemOpLowering()
248 NewVT = MVT::f64; in findOptimalMemOpLowering()
255 NewVT = (MVT::SimpleValueType)(NewVT.getSimpleVT().SimpleTy - 1); in findOptimalMemOpLowering()
256 if (NewVT == MVT::i8) in findOptimalMemOpLowering()
258 } while (!isSafeMemOpType(NewVT.getSimpleVT())); in findOptimalMemOpLowering()
260 NewVTSize = NewVT.getSizeInBits() / 8; in findOptimalMemOpLowering()
[all …]
H A DLegalizeDAG.cpp3083 EVT NewVT = in ExpandNode() local
3086 assert(NewVT.bitsEq(VT)); in ExpandNode()
3089 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0); in ExpandNode()
3090 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1); in ExpandNode()
3094 NewVT.getVectorNumElements()/VT.getVectorNumElements(); in ExpandNode()
3110 VT = NewVT; in ExpandNode()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1134 MVT NewVT = MVT::getVectorVT(EltTy, EC); in getVectorTypeBreakdownMVT() local
1135 if (!TLI->isTypeLegal(NewVT)) in getVectorTypeBreakdownMVT()
1136 NewVT = EltTy; in getVectorTypeBreakdownMVT()
1137 IntermediateVT = NewVT; in getVectorTypeBreakdownMVT()
1139 unsigned LaneSizeInBits = NewVT.getScalarSizeInBits(); in getVectorTypeBreakdownMVT()
1145 MVT DestVT = TLI->getRegisterType(NewVT); in getVectorTypeBreakdownMVT()
1147 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdownMVT()
1621 EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt); in getVectorTypeBreakdown() local
1622 if (!isTypeLegal(NewVT)) in getVectorTypeBreakdown()
1623 NewVT = EltTy; in getVectorTypeBreakdown()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/BPF/
H A DBPFISelLowering.h129 EVT NewVT) const override { in shouldReduceLoadWidth() argument
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp392 MVT NewVT = TLI.getRegisterTypeForCallingConv(Ctx, CC, SplitEVTs[i]); in lowerReturn() local
393 if (EVT(NewVT) != SplitEVTs[i]) { in lowerReturn()
400 LLT NewLLT(NewVT); in lowerReturn()
402 CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx); in lowerReturn()
405 if (NewVT.isVector()) { in lowerReturn()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp598 MVT NewVT = TLI->getRegisterTypeForCallingConv(Ctx, CallConv, CurVT); in determineAssignments() local
607 if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i], in determineAssignments()
638 if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i], in determineAssignments()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp697 EVT NewVT) const { in shouldReduceLoadWidth()
699 if (!TargetLoweringBase::shouldReduceLoadWidth(N, ExtTy, NewVT)) in shouldReduceLoadWidth()
702 unsigned NewSize = NewVT.getStoreSizeInBits(); in shouldReduceLoadWidth()
1366 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, in LowerCONCAT_VECTORS() local
1368 SDValue BV = DAG.getBuildVector(NewVT, SL, Args); in LowerCONCAT_VECTORS()
3019 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in performLoadCombine() local
3022 = DAG.getLoad(NewVT, SL, LN->getChain(), in performLoadCombine()
3070 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in performStoreCombine() local
3076 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val); in performStoreCombine()
H A DR600ISelLowering.cpp1702 EVT NewVT = MVT::v4i32; in constBufferLoad() local
1705 NewVT = VT; in constBufferLoad()
1708 SDValue Result = DAG.getBuildVector(NewVT, DL, ArrayRef(Slots, NumElements)); in constBufferLoad()
H A DSIISelLowering.cpp5099 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in ReplaceNodeResults() local
5100 SDValue LHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(1)); in ReplaceNodeResults()
5101 SDValue RHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(2)); in ReplaceNodeResults()
5103 EVT SelectVT = NewVT; in ReplaceNodeResults()
5104 if (NewVT.bitsLT(MVT::i32)) { in ReplaceNodeResults()
5113 if (NewVT != SelectVT) in ReplaceNodeResults()
5114 NewSelect = DAG.getNode(ISD::TRUNCATE, SL, NewVT, NewSelect); in ReplaceNodeResults()
6628 EVT NewVT = NumVDataDwords > 1 ? in lowerImage() local
6632 ResultTypes[0] = NewVT; in lowerImage()
10872 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VecVT); in performExtractVectorEltCombine() local
[all …]
H A DAMDGPUISelDAGToDAG.cpp679 MVT NewVT = Opc == AMDGPUISD::CVT_PKRTZ_F16_F32 ? MVT::v2f16 : MVT::v2i16; in Select() local
680 N = CurDAG->MorphNodeTo(N, N->getOpcode(), CurDAG->getVTList(NewVT), in Select()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h343 EVT NewVT) const override;
H A DHexagonISelLowering.cpp3807 ISD::LoadExtType ExtTy, EVT NewVT) const { in shouldReduceLoadWidth()
3809 if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT)) in shouldReduceLoadWidth()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h612 EVT NewVT) const override;
H A DAArch64ISelLowering.cpp3912 MVT NewVT = MVT::getVectorVT(MVT::f32, NumElts); in LowerVectorFP_TO_INT() local
3915 SDValue Ext = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {NewVT, MVT::Other}, in LowerVectorFP_TO_INT()
3922 DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0))); in LowerVectorFP_TO_INT()
4353 EVT NewVT = getExtensionTo64Bits(OrigTy); in addRequiredExtensionForVectorMULL() local
4355 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N); in addRequiredExtensionForVectorMULL()
11383 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2); in tryWidenMaskForShuffle() local
11384 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) { in tryWidenMaskForShuffle()
11385 V0 = DAG.getBitcast(NewVT, V0); in tryWidenMaskForShuffle()
11386 V1 = DAG.getBitcast(NewVT, V1); in tryWidenMaskForShuffle()
11388 DAG.getVectorShuffle(NewVT, DL, V0, V1, NewMask)); in tryWidenMaskForShuffle()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86ISelLowering.h1395 EVT NewVT) const override;
H A DX86ISelLowering.cpp5806 EVT NewVT) const { in shouldReduceLoadWidth()
10278 MVT NewVT = V0_LO.getSimpleValueType(); in ExpandHorizontalBinOp() local
10280 SDValue LO = DAG.getUNDEF(NewVT); in ExpandHorizontalBinOp()
10281 SDValue HI = DAG.getUNDEF(NewVT); in ExpandHorizontalBinOp()
10286 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI); in ExpandHorizontalBinOp()
10288 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI); in ExpandHorizontalBinOp()
10292 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO); in ExpandHorizontalBinOp()
10295 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI); in ExpandHorizontalBinOp()
14494 MVT NewVT = V.getSimpleValueType(); in getScalarValueForVectorElement() local
14495 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) in getScalarValueForVectorElement()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Transforms/InstCombine/
H A DInstCombineCalls.cpp2161 VectorType *NewVT = cast<VectorType>(II->getType()); in visitCallInst() local
2164 CV0 = ConstantExpr::getIntegerCast(CV0, NewVT, /*isSigned=*/!Zext); in visitCallInst()
2165 CV1 = ConstantExpr::getIntegerCast(CV1, NewVT, /*isSigned=*/!Zext); in visitCallInst()
/openbsd-src/gnu/llvm/clang/lib/AST/
H A DDecl.cpp2662 auto *NewVT = VarTemplate->getInstantiatedFromMemberTemplate(); in getTemplateInstantiationPattern() local
2663 if (!NewVT) in getTemplateInstantiationPattern()
2665 VarTemplate = NewVT; in getTemplateInstantiationPattern()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DTargetLowering.h1636 EVT NewVT) const { in shouldReduceLoadWidth() argument
1639 if (NewVT.isVector() && !Load->hasOneUse()) in shouldReduceLoadWidth()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp8526 EVT NewVT = getVectorTyFromPredicateVector(VT); in PromoteMVEPredVector() local
8544 return DAG.getNode(ISD::BITCAST, dl, NewVT, PredAsVector); in PromoteMVEPredVector()
8576 EVT NewVT = PredAsVector1.getValueType(); in LowerVECTOR_SHUFFLE_i1() local
8577 SDValue PredAsVector2 = V2.isUndef() ? DAG.getUNDEF(NewVT) in LowerVECTOR_SHUFFLE_i1()
8579 assert(PredAsVector2.getValueType() == NewVT && in LowerVECTOR_SHUFFLE_i1()
8583 SDValue Shuffled = DAG.getVectorShuffle(NewVT, dl, PredAsVector1, in LowerVECTOR_SHUFFLE_i1()
9099 EVT NewVT = NewV.getValueType(); in LowerCONCAT_VECTORS_i1() local
9101 for (unsigned i = 0, e = NewVT.getVectorNumElements(); i < e; i++, j++) { in LowerCONCAT_VECTORS_i1()
9434 EVT NewVT = getExtensionTo64Bits(OrigTy); in AddRequiredExtensionForVMULL() local
9436 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N); in AddRequiredExtensionForVMULL()
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp3639 MVT NewVT = in expandUnalignedRVVLoad() local
3641 assert(NewVT.isValid() && in expandUnalignedRVVLoad()
3643 SDValue L = DAG.getLoad(NewVT, DL, Load->getChain(), Load->getBasePtr(), in expandUnalignedRVVLoad()
3670 MVT NewVT = in expandUnalignedRVVStore() local
3672 assert(NewVT.isValid() && in expandUnalignedRVVStore()
3674 StoredVal = DAG.getBitcast(NewVT, StoredVal); in expandUnalignedRVVStore()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp14224 EVT NewVT = TargetVT == MVT::v2i64 ? MVT::v2f64 : MVT::v4f32; in combineElementTruncationToVectorTruncation() local
14225 SDValue BV = DAG.getBuildVector(NewVT, dl, Ops); in combineElementTruncationToVectorTruncation()