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Searched refs:MicroOpBufferSize (Results 1 – 25 of 61) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/include/llvm/MC/
H A DMCSchedule.h273 unsigned MicroOpBufferSize; member
333 bool isOutOfOrder() const { return MicroOpBufferSize > 1; } in isOutOfOrder()
/openbsd-src/gnu/llvm/llvm/tools/llvm-mca/Views/
H A DRetireControlUnitStatistics.cpp23 TotalROBEntries = SM.MicroOpBufferSize; in RetireControlUnitStatistics()
H A DTimelineView.cpp171 getSubTargetInfo().getSchedModel().MicroOpBufferSize); in printWaitTimeEntry()
/openbsd-src/gnu/llvm/llvm/lib/MCA/HardwareUnits/
H A DRetireControlUnit.cpp24 AvailableEntries(SM.isOutOfOrder() ? SM.MicroOpBufferSize : 0), in RetireControlUnit()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h160 unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; } in getMicroOpBufferSize()
/openbsd-src/gnu/llvm/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td48 let MicroOpBufferSize = 0;
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSISchedule.td74 // MicroOpBufferSize = 1 means that instructions will always be added
77 let MicroOpBufferSize = 1;
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td20 let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer.
H A DAArch64SchedKryo.td21 let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer
H A DAArch64SchedThunderX.td22 let MicroOpBufferSize = 0; // ThunderX T88/T81/T83 are in-order.
H A DAArch64SchedA53.td19 let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order.
H A DAArch64SchedA55.td22 let MicroOpBufferSize = 0; // The Cortex-A55 is an in-order processor
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVSchedSyntacoreSCR1.td19 let MicroOpBufferSize = 0;
H A DRISCVSchedSiFive7.td13 let MicroOpBufferSize = 0; // Explicitly set to zero since SiFive7 is in-order.
H A DRISCVSchedRocket.td15 let MicroOpBufferSize = 0; // Rocket is in-order.
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMScheduleM4.td15 let MicroOpBufferSize = 0; // In-order
H A DARMScheduleM7.td15 let MicroOpBufferSize = 0; // The Cortex-M7 is in-order.
H A DARMScheduleM55.td85 let MicroOpBufferSize = 0; // Explicitly set to zero since M55 is in-order.
/openbsd-src/gnu/llvm/llvm/include/llvm/Target/
H A DTargetSchedule.td78 int MicroOpBufferSize = -1; // Max micro-ops that can be buffered.
155 // MicroOpBufferSize, which should be the minimum size of either the
555 // field MicroOpBufferSize in SchedModel if the reorder buffer size is unknown.
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCScheduleP10.td30 let MicroOpBufferSize = 44;
H A DPPCScheduleP9.td37 let MicroOpBufferSize = 44;
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86Schedule.td725 // MicroOpBufferSize > 1 indicates that RAW dependencies can be
739 let MicroOpBufferSize = 32;
H A DX86ScheduleSLM.td18 let MicroOpBufferSize = 32; // Based on the reorder buffer.
H A DX86ScheduleZnver1.td17 // Based on the reorder buffer we define MicroOpBufferSize
18 let MicroOpBufferSize = 192;
H A DX86ScheduleZnver2.td17 // Based on the reorder buffer we define MicroOpBufferSize
18 let MicroOpBufferSize = 224;

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