Searched refs:MaxVGPRs (Results 1 – 4 of 4) sorted by relevance
76 unsigned MaxVGPRs; member in __anon682394fa0111::AMDGPUPromoteAllocaImpl180 MaxVGPRs = ST.getMaxNumVGPRs(ST.getWavesPerEU(F).first); in run()184 MaxVGPRs = std::min(MaxVGPRs, 32u); in run()186 MaxVGPRs = 128; in run()388 unsigned MaxVGPRs) { in tryPromoteAllocaToVector() argument405 : (MaxVGPRs * 32); in tryPromoteAllocaToVector()409 << MaxVGPRs << " registers available\n"); in tryPromoteAllocaToVector()941 if (tryPromoteAllocaToVector(&I, DL, MaxVGPRs)) in handleAlloca()1158 bool handlePromoteAllocaToVector(AllocaInst &I, unsigned MaxVGPRs) { in handlePromoteAllocaToVector() argument1167 return tryPromoteAllocaToVector(&I, Mod->getDataLayout(), MaxVGPRs); in handlePromoteAllocaToVector()[all …]
76 unsigned MaxVGPRs; member in __anon425b70c30111::SIFormMemoryClauses209 MaxPressure.getVGPRNum(ST->hasGFX90AInsts()) <= MaxVGPRs / 2 && in checkPressure()275 MaxVGPRs = TRI->getAllocatableSet(MF, &AMDGPU::VGPR_32RegClass).count(); in runOnMachineFunction()
938 unsigned MaxVGPRs = ST.getMaxNumVGPRs(MF); in checkScheduling() local940 if (PressureAfter.getVGPRNum(false) > MaxVGPRs || in checkScheduling()941 PressureAfter.getAGPRNum() > MaxVGPRs || in checkScheduling()
623 unsigned MaxVGPRs = RI.getRegPressureLimit(&AMDGPU::VGPR_32RegClass, in indirectCopyToAGPR() local639 if (!Tmp2 || RI.getHWRegIndex(Tmp2) >= MaxVGPRs) in indirectCopyToAGPR()