| /openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVExpandAtomicPseudoInsts.cpp | 259 Register MaskReg, Register ScratchReg) { in insertMaskedMerge() argument
261 assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); in insertMaskedMerge()
262 assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); in insertMaskedMerge()
272 .addReg(MaskReg); in insertMaskedMerge()
287 Register MaskReg = MI.getOperand(4).getReg(); in doMaskedAtomicBinOpExpansion() local
329 insertMaskedMerge(TII, DL, LoopMBB, ScratchReg, DestReg, ScratchReg, MaskReg, in doMaskedAtomicBinOpExpansion()
427 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicMinMaxOp() local
443 .addReg(MaskReg); in expandAtomicMinMaxOp()
486 MaskReg, Scratch1Reg); in expandAtomicMinMaxOp()
525 Register MaskReg, in tryToFoldBNEOnCmpXchgResult() argument
[all …]
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| /openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchExpandAtomicPseudoInsts.cpp | 227 Register MaskReg, Register ScratchReg) { in insertMaskedMerge() argument
229 assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); in insertMaskedMerge()
230 assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); in insertMaskedMerge()
238 .addReg(MaskReg); in insertMaskedMerge()
253 Register MaskReg = MI.getOperand(4).getReg(); in doMaskedAtomicBinOpExpansion() local
300 insertMaskedMerge(TII, DL, LoopMBB, ScratchReg, DestReg, ScratchReg, MaskReg, in doMaskedAtomicBinOpExpansion()
401 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicMinMaxOp() local
415 .addReg(MaskReg); in expandAtomicMinMaxOp()
461 MaskReg, Scratch1Reg); in expandAtomicMinMaxOp()
562 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicCmpXchg() local
[all …]
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 101 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask() argument
107 MaskInst.addOperand(MCOperand::createReg(MaskReg)); in emitMask()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 221 Register MaskReg = getMRI()->createGenericVirtualRegister(MaskTy); in buildMaskLowPtrBits() local
222 buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits)); in buildMaskLowPtrBits()
223 return buildPtrMask(Res, Op0, MaskReg); in buildMaskLowPtrBits()
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| H A D | LegalizerHelper.cpp | 7476 Register MaskReg = MI.getOperand(1).getReg(); in lowerSelect() local
7480 LLT MaskTy = MRI.getType(MaskReg); in lowerSelect()
7496 Register MaskElt = MaskReg; in lowerSelect()
7509 MaskReg = ShufSplat.getReg(0); in lowerSelect()
7517 auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg); in lowerSelect()
7518 auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg); in lowerSelect()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.h | 371 bool optimizePTestInstr(MachineInstr *PTest, unsigned MaskReg,
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| H A D | AArch64InstrInfo.cpp | 1302 MachineInstr *PTest, unsigned MaskReg, unsigned PredReg, in optimizePTestInstr() argument
1304 auto *Mask = MRI->getUniqueVRegDef(MaskReg); in optimizePTestInstr()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 2789 Register MaskReg = I.getOperand(2).getReg(); in selectG_PTRMASK() local
2791 LLT MaskTy = MRI->getType(MaskReg); in selectG_PTRMASK()
2797 const RegisterBank *MaskRB = RBI.getRegBank(MaskReg, *MRI, TRI); in selectG_PTRMASK()
2804 APInt MaskOnes = KnownBits->getKnownOnes(MaskReg).zext(64); in selectG_PTRMASK()
2815 .addReg(MaskReg); in selectG_PTRMASK()
2831 !RBI.constrainGenericRegister(MaskReg, *MaskRC, *MRI)) in selectG_PTRMASK()
2840 .addReg(MaskReg); in selectG_PTRMASK()
2865 .addReg(MaskReg, 0, AMDGPU::sub0); in selectG_PTRMASK()
2879 .addReg(MaskReg, 0, AMDGPU::sub1); in selectG_PTRMASK()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 11774 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary() local
11850 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) in EmitPartwordAtomicBinary()
11864 .addReg(MaskReg); in EmitPartwordAtomicBinary()
11865 BuildMI(BB, dl, TII->get(PPC::AND), Tmp3Reg).addReg(TmpReg).addReg(MaskReg); in EmitPartwordAtomicBinary()
11873 .addReg(MaskReg); in EmitPartwordAtomicBinary()
12769 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitInstrWithCustomInserter() local
12854 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) in EmitInstrWithCustomInserter()
12859 .addReg(MaskReg); in EmitInstrWithCustomInserter()
12862 .addReg(MaskReg); in EmitInstrWithCustomInserter()
12870 .addReg(MaskReg); in EmitInstrWithCustomInserter()
[all …]
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3096 Register MaskReg = I.getOperand(2).getReg(); in select() local
3097 std::optional<int64_t> MaskVal = getIConstantVRegSExtVal(MaskReg, MRI); in select()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 5018 Register MaskReg = MIB.getReg(1); in expandPostRAPseudo() local
5026 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState) in expandPostRAPseudo()
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