Home
last modified time | relevance | path

Searched refs:MachineInstr (Results 1 – 25 of 859) sorted by relevance

12345678910>>...35

/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h38 class MachineInstr; variable
52 MachineInstr *MI;
74 MachineInstr *Logic;
75 MachineInstr *Shift2;
162 void replaceOpcodeWith(MachineInstr &FromMI, unsigned ToOpcode) const;
178 bool tryCombineCopy(MachineInstr &MI);
179 bool matchCombineCopy(MachineInstr &MI);
180 void applyCombineCopy(MachineInstr &MI);
184 bool isPredecessor(const MachineInstr &DefMI, const MachineInstr &UseMI);
192 bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI);
[all …]
H A DLegalizerHelper.h36 class MachineInstr; variable
90 LegalizeResult legalizeInstrStep(MachineInstr &MI,
94 LegalizeResult libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver);
98 LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
103 LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
106 LegalizeResult bitcast(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
110 LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
114 LegalizeResult fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
119 LegalizeResult moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
133 void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx,
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h34 class MachineInstr; variable
57 unsigned isLoadFromStackSlot(const MachineInstr &MI,
65 unsigned isStoreToStackSlot(const MachineInstr &MI,
72 const MachineInstr &MI,
79 const MachineInstr &MI,
205 bool expandPostRAPseudo(MachineInstr &MI) const override;
209 const MachineInstr &LdSt,
224 bool isPredicated(const MachineInstr &MI) const override;
227 bool isPostIncrement(const MachineInstr &MI) const override;
231 bool PredicateInstruction(MachineInstr &MI,
[all …]
H A DHexagonVLIWPacketizer.h23 class MachineInstr; variable
29 std::vector<MachineInstr *> OldPacketMIs;
54 std::vector<MachineInstr*> IgnoreDepMIs;
89 bool ignorePseudoInstruction(const MachineInstr &MI,
94 bool isSoloInstruction(const MachineInstr &MI) override;
105 MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override;
108 bool shouldAddToPacket(const MachineInstr &MI) override;
119 bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
121 bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
124 bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU,
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.h25 class MachineInstr; variable
34 typedef function_ref<bool(const MachineInstr &)> IsHazardFn;
43 MachineInstr *CurrCycleInstr;
44 std::list<MachineInstr*> EmittedInstrs;
63 void addClauseInst(const MachineInstr &MI);
67 unsigned getMFMAPipelineWaitStates(const MachineInstr &MI) const;
75 void runOnInstruction(MachineInstr *MI);
81 int checkSoftClauseHazards(MachineInstr *SMEM);
82 int checkSMRDHazards(MachineInstr *SMRD);
83 int checkVMEMHazards(MachineInstr* VMEM);
[all …]
H A DAMDGPUInstructionSelector.h38 class MachineInstr; variable
57 bool select(MachineInstr &I) override;
73 bool isInstrUniform(const MachineInstr &MI) const;
81 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
87 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
88 bool selectCOPY(MachineInstr &I) const;
89 bool selectPHI(MachineInstr &I) const;
90 bool selectG_TRUNC(MachineInstr &I) const;
91 bool selectG_SZA_EXT(MachineInstr &I) const;
92 bool selectG_CONSTANT(MachineInstr &I) const;
[all …]
H A DAMDGPULegalizerInfo.h38 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
44 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
46 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
48 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
50 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
52 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
54 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
56 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
58 bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
59 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
[all …]
H A DSIInstrInfo.h62 using SetVectorType = SmallSetVector<MachineInstr *, 32>;
81 void swapOperands(MachineInstr &Inst) const;
84 moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
87 void lowerSelect(SetVectorType &Worklist, MachineInstr &Inst,
91 MachineInstr &Inst) const;
94 MachineInstr &Inst) const;
97 MachineInstr &Inst,
101 MachineInstr &Inst,
105 MachineInstr &Inst, unsigned Opcode,
108 void splitScalar64BitAddSub(SetVectorType &Worklist, MachineInstr &Inst,
[all …]
H A DR600InstrInfo.h34 class MachineInstr; variable
44 ExtractSrcs(MachineInstr &MI, const DenseMap<unsigned, unsigned> &PV,
91 bool canBeConsideredALU(const MachineInstr &MI) const;
94 bool isTransOnly(const MachineInstr &MI) const;
96 bool isVectorOnly(const MachineInstr &MI) const;
100 bool usesVertexCache(const MachineInstr &MI) const;
102 bool usesTextureCache(const MachineInstr &MI) const;
105 bool usesAddressRegister(MachineInstr &MI) const;
106 bool definesAddressRegister(MachineInstr &MI) const;
107 bool readsLDSSrcReg(const MachineInstr &MI) const;
[all …]
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h130 bool isTriviallyReMaterializable(const MachineInstr &MI) const { in isTriviallyReMaterializable()
151 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const { in isReallyTriviallyReMaterializable()
170 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
193 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI) const;
205 bool isFrameInstr(const MachineInstr &I) const { in isFrameInstr()
211 bool isFrameSetup(const MachineInstr &I) const { in isFrameSetup()
223 int64_t getFrameSize(const MachineInstr &I) const { in getFrameSize()
232 int64_t getFrameTotalSize(const MachineInstr &I) const { in getFrameTotalSize()
248 virtual int getSPAdjust(const MachineInstr &MI) const;
255 virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, in isCoalescableExtInstr()
[all …]
H A DReachingDefAnalysis.h34 class MachineInstr; variable
94 DenseMap<MachineInstr *, int> InstIds;
107 using InstSet = SmallPtrSetImpl<MachineInstr*>;
142 int getReachingDef(MachineInstr *MI, MCRegister PhysReg) const;
145 bool hasSameReachingDef(MachineInstr *A, MachineInstr *B,
150 bool isReachingDefLiveOut(MachineInstr *MI, MCRegister PhysReg) const;
154 MachineInstr *getLocalLiveOutMIDef(MachineBasicBlock *MBB,
159 MachineInstr *getUniqueReachingMIDef(MachineInstr *MI,
164 MachineInstr *getMIOperand(MachineInstr *MI, unsigned Idx) const;
168 MachineInstr *getMIOperand(MachineInstr *MI, MachineOperand &MO) const;
[all …]
H A DModuloSchedule.h74 class MachineInstr; variable
87 std::vector<MachineInstr *> ScheduledInstrs;
90 DenseMap<MachineInstr *, int> Cycle;
93 DenseMap<MachineInstr *, int> Stage;
107 std::vector<MachineInstr *> ScheduledInstrs, in ModuloSchedule()
108 DenseMap<MachineInstr *, int> Cycle, in ModuloSchedule() argument
109 DenseMap<MachineInstr *, int> Stage) in ModuloSchedule()
134 int getStage(MachineInstr *MI) { in getStage()
140 int getCycle(MachineInstr *MI) { in getCycle()
146 void setStage(MachineInstr *MI, int MIStage) { in setStage()
[all …]
H A DLiveVariables.h90 std::vector<MachineInstr*> Kills;
95 bool removeKill(MachineInstr &MI) { in removeKill()
96 std::vector<MachineInstr *>::iterator I = find(Kills, &MI); in removeKill()
104 MachineInstr *findKill(const MachineBasicBlock *MBB) const;
136 std::vector<MachineInstr *> PhysRegDef;
141 std::vector<MachineInstr *> PhysRegUse;
147 DenseMap<MachineInstr*, unsigned> DistanceMap;
152 bool HandlePhysRegKill(Register Reg, MachineInstr *MI);
157 void HandlePhysRegUse(Register Reg, MachineInstr &MI);
158 void HandlePhysRegDef(Register Reg, MachineInstr *MI,
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstrInfo.h33 AC_EVEX_2_VEX = MachineInstr::TAsmComments
49 CondCode getCondFromMI(const MachineInstr &MI);
52 CondCode getCondFromBranch(const MachineInstr &MI);
55 CondCode getCondFromSETCC(const MachineInstr &MI);
58 CondCode getCondFromCMov(const MachineInstr &MI);
77 bool isX87Instruction(MachineInstr &MI);
118 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) { in isLeaMem()
131 inline static bool isMem(const MachineInstr &MI, unsigned Op) { in isMem()
147 SmallVectorImpl<MachineInstr *> &CondBranches,
161 int64_t getFrameAdjustment(const MachineInstr &I) const { in getFrameAdjustment()
[all …]
H A DX86AsmPrinter.h82 void LowerSTACKMAP(const MachineInstr &MI);
83 void LowerPATCHPOINT(const MachineInstr &MI, X86MCInstLower &MCIL);
84 void LowerSTATEPOINT(const MachineInstr &MI, X86MCInstLower &MCIL);
85 void LowerFAULTING_OP(const MachineInstr &MI, X86MCInstLower &MCIL);
86 void LowerPATCHABLE_OP(const MachineInstr &MI, X86MCInstLower &MCIL);
88 void LowerTlsAddr(X86MCInstLower &MCInstLowering, const MachineInstr &MI);
91 void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
93 void LowerPATCHABLE_RET(const MachineInstr &MI, X86MCInstLower &MCIL);
94 void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
95 void LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.h52 unsigned isLoadFromStackSlot(const MachineInstr &MI,
54 unsigned isStoreToStackSlot(const MachineInstr &MI,
75 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
85 MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
87 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
110 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
115 bool analyzeSelect(const MachineInstr &MI,
119 MachineInstr *optimizeSelect(MachineInstr &MI,
120 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
123 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
[all …]
H A DRISCVMergeBaseOffset.cpp36 bool detectFoldable(MachineInstr &Hi, MachineInstr *&Lo);
38 bool detectAndFoldOffset(MachineInstr &Hi, MachineInstr &Lo);
39 void foldOffset(MachineInstr &Hi, MachineInstr &Lo, MachineInstr &Tail,
41 bool foldLargeOffset(MachineInstr &Hi, MachineInstr &Lo,
42 MachineInstr &TailAdd, Register GSReg);
43 bool foldShiftedOffset(MachineInstr &Hi, MachineInstr &Lo,
44 MachineInstr &TailShXAdd, Register GSReg);
46 bool foldIntoMemoryOps(MachineInstr &Hi, MachineInstr &Lo);
89 bool RISCVMergeBaseOffsetOpt::detectFoldable(MachineInstr &Hi, in INITIALIZE_PASS()
90 MachineInstr *&Lo) { in INITIALIZE_PASS()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsRegisterBankInfo.h39 getInstrMapping(const MachineInstr &MI) const override;
50 void setRegBank(MachineInstr &MI, MachineRegisterInfo &MRI) const;
125 SmallVector<MachineInstr *, 2> DefUses;
126 SmallVector<MachineInstr *, 2> UseDefs;
136 MachineInstr *skipCopiesOutgoing(MachineInstr *MI) const;
143 MachineInstr *skipCopiesIncoming(MachineInstr *MI) const;
146 AmbiguousRegDefUseContainer(const MachineInstr *MI);
147 SmallVectorImpl<MachineInstr *> &getDefUses() { return DefUses; } in getDefUses()
148 SmallVectorImpl<MachineInstr *> &getUseDefs() { return UseDefs; } in getUseDefs()
156 DenseMap<const MachineInstr *, SmallVector<const MachineInstr *, 2>>
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h222 SmallVectorImpl<MachineInstr *> &NewMIs) const;
226 SmallVectorImpl<MachineInstr *> &NewMIs) const;
230 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
231 unsigned OpNoForForwarding, MachineInstr **KilledDef) const;
234 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
238 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
240 MachineInstr &DefMI) const;
243 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
244 unsigned ConstantOpNo, MachineInstr &DefMI,
251 MachineInstr *getForwardingDefMI(MachineInstr &MI,
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h47 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
49 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
51 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
55 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
56 const MachineInstr &MIb) const override;
58 unsigned isLoadFromStackSlot(const MachineInstr &MI,
60 unsigned isStoreToStackSlot(const MachineInstr &MI,
64 static bool isGPRZero(const MachineInstr &MI);
67 static bool isGPRCopy(const MachineInstr &MI);
70 static bool isFPRCopy(const MachineInstr &MI);
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp77 MachineInstr *tryToCombine(MachineInstr &Ldst);
80 bool noUseOfAddBeforeLoadOrStore(const MachineInstr *Add,
81 const MachineInstr *Ldst);
85 bool canHoistLoadStoreTo(MachineInstr *Ldst, MachineInstr *To);
95 MachineInstr *canJoinInstructions(MachineInstr *Ldst, MachineInstr *Add,
96 SmallVectorImpl<MachineInstr *> *Uses);
100 bool canFixPastUses(const ArrayRef<MachineInstr *> &Uses,
105 void fixPastUses(ArrayRef<MachineInstr *> Uses, unsigned BaseReg,
111 void changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
134 static bool isAddConstantOp(const MachineInstr &MI, int64_t &Amount) { in isAddConstantOp()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.h31 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
34 MachineInstr &MI) const override;
37 bool legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI,
39 bool legalizeLoadStore(MachineInstr &MI, MachineRegisterInfo &MRI,
42 bool legalizeShlAshrLshr(MachineInstr &MI, MachineRegisterInfo &MRI,
46 bool legalizeSmallCMGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeVectorTrunc(MachineInstr &MI, LegalizerHelper &Helper) const;
50 bool legalizeShuffleVector(MachineInstr &MI, LegalizerHelper &Helper) const;
51 bool legalizeBitfieldExtract(MachineInstr &MI, MachineRegisterInfo &MRI,
53 bool legalizeRotate(MachineInstr &MI, MachineRegisterInfo &MRI,
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h61 const MachineInstr &MI, unsigned DefIdx,
74 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
90 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
101 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
108 isCopyInstrImpl(const MachineInstr &MI) const override;
113 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
123 MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
157 bool isPredicated(const MachineInstr &MI) const override;
161 createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
165 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const { in getPredicate()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.h180 void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,
182 void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
184 void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
186 void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
188 void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
190 void expandLoadStackGuard(MachineInstr *MI) const;
212 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
220 unsigned isLoadFromStackSlot(const MachineInstr &MI,
222 unsigned isStoreToStackSlot(const MachineInstr &MI,
224 bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
[all …]
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DImplicitNullChecks.cpp81 static bool canHandle(const MachineInstr *MI);
86 bool canReorder(const MachineInstr *A, const MachineInstr *B);
99 std::optional<ArrayRef<MachineInstr *>::iterator> PotentialDependence;
103 std::optional<ArrayRef<MachineInstr *>::iterator> PotentialDependence) in DependenceResult()
115 DependenceResult computeDependence(const MachineInstr *MI,
116 ArrayRef<MachineInstr *> Block);
121 MachineInstr *MemOperation;
124 MachineInstr *CheckOperation;
137 MachineInstr *OnlyDependency;
140 explicit NullCheck(MachineInstr *memOperation, MachineInstr *checkOperation, in NullCheck()
[all …]

12345678910>>...35