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Searched refs:MRI (Results 1 – 25 of 673) sorted by relevance

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/openbsd-src/gnu/usr.bin/binutils/ld/
H A Dldlex.l122 %s MRI
151 <MRI,EXPRESSION>"$"([0-9A-Fa-f])+ {
157 <MRI,EXPRESSION>([0-9A-Fa-f])+(H|h|X|x|B|b|O|o|D|d) {
182 <SCRIPT,DEFSYMEXP,MRI,BOTH,EXPRESSION>((("$"|0[xX])([0-9A-Fa-f])+)|(([0-9])+))(M|K|m|k)? {
211 <BOTH,SCRIPT,EXPRESSION,MRI>"]" { RTOKEN(']');}
212 <BOTH,SCRIPT,EXPRESSION,MRI>"[" { RTOKEN('[');}
213 <BOTH,SCRIPT,EXPRESSION,MRI>"<<=" { RTOKEN(LSHIFTEQ);}
214 <BOTH,SCRIPT,EXPRESSION,MRI>">>=" { RTOKEN(RSHIFTEQ);}
215 <BOTH,SCRIPT,EXPRESSION,MRI>"||" { RTOKEN(OROR);}
216 <BOTH,SCRIPT,EXPRESSION,MRI>"==" { RTOKEN(EQ);}
[all …]
/openbsd-src/gnu/usr.bin/binutils-2.17/ld/
H A Dldlex.l119 %s MRI
148 <MRI,EXPRESSION>"$"([0-9A-Fa-f])+ {
154 <MRI,EXPRESSION>([0-9A-Fa-f])+(H|h|X|x|B|b|O|o|D|d) {
179 <SCRIPT,DEFSYMEXP,MRI,BOTH,EXPRESSION>((("$"|0[xX])([0-9A-Fa-f])+)|(([0-9])+))(M|K|m|k)? {
208 <BOTH,SCRIPT,EXPRESSION,MRI>"]" { RTOKEN(']');}
209 <BOTH,SCRIPT,EXPRESSION,MRI>"[" { RTOKEN('[');}
210 <BOTH,SCRIPT,EXPRESSION,MRI>"<<=" { RTOKEN(LSHIFTEQ);}
211 <BOTH,SCRIPT,EXPRESSION,MRI>">>=" { RTOKEN(RSHIFTEQ);}
212 <BOTH,SCRIPT,EXPRESSION,MRI>"||" { RTOKEN(OROR);}
213 <BOTH,SCRIPT,EXPRESSION,MRI>"==" { RTOKEN(EQ);}
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h41 MachineRegisterInfo &MRI,
44 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
46 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
48 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
50 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
52 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
54 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
56 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
59 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
61 bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
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H A DAMDGPURegisterBankInfo.cpp101 MachineRegisterInfo &MRI; member in __anon2a3621150111::ApplyRegBankMapping
108 : RBI(RBI_), MRI(MRI_), NewBank(RB) {} in ApplyRegBankMapping()
125 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, MRI, *RBI.TRI); in applyBank()
128 assert(MRI.getType(SrcReg) == LLT::scalar(1)); in applyBank()
129 assert(MRI.getType(DstReg) == S32); in applyBank()
138 MRI.setRegBank(True.getReg(0), *NewBank); in applyBank()
139 MRI.setRegBank(False.getReg(0), *NewBank); in applyBank()
143 assert(!MRI.getRegClassOrRegBank(DstReg)); in applyBank()
144 MRI.setRegBank(DstReg, *NewBank); in applyBank()
151 const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI); in applyBank()
[all …]
H A DAMDGPURegisterBankInfo.h53 MachineRegisterInfo &MRI,
60 MachineRegisterInfo &MRI) const;
62 Register buildReadFirstLane(MachineIRBuilder &B, MachineRegisterInfo &MRI,
67 MachineRegisterInfo &MRI,
70 MachineRegisterInfo &MRI,
73 void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI,
77 MachineRegisterInfo &MRI) const;
80 MachineRegisterInfo &MRI) const;
84 MachineRegisterInfo &MRI, int RSrcIdx) const;
91 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
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H A DGCNRegPressure.cpp39 const MachineRegisterInfo &MRI) { in getRegKind() argument
41 const auto RC = MRI.getRegClass(Reg); in getRegKind()
42 auto STI = static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo()); in getRegKind()
53 const MachineRegisterInfo &MRI) { in inc() argument
64 switch (auto Kind = getRegKind(Reg, MRI)) { in inc()
81 Value[Kind] += Sign * MRI.getPressureSets(Reg).getWeight(); in inc()
159 const MachineRegisterInfo &MRI) { in getDefRegMask() argument
166 MRI.getMaxLaneMaskForVReg(MO.getReg()) : in getDefRegMask()
167 MRI.getTargetRegisterInfo()->getSubRegIndexLaneMask(MO.getSubReg()); in getDefRegMask()
171 const MachineRegisterInfo &MRI, in getUsedRegMask() argument
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H A DAMDGPUCombinerHelper.cpp68 const MachineRegisterInfo &MRI) { in opMustUseVOP3Encoding() argument
71 MRI.getType(MI.getOperand(0).getReg()).getScalarSizeInBits() == 64; in opMustUseVOP3Encoding()
113 static bool allUsesHaveSourceMods(MachineInstr &MI, MachineRegisterInfo &MRI, in allUsesHaveSourceMods() argument
122 for (const MachineInstr &Use : MRI.use_nodbg_instructions(Dst)) { in allUsesHaveSourceMods()
126 if (!opMustUseVOP3Encoding(Use, MRI)) { in allUsesHaveSourceMods()
152 MachineRegisterInfo &MRI) { in isConstantCostlierToNegate() argument
154 if (mi_match(Reg, MRI, m_GFCstOrSplat(FPValReg))) { in isConstantCostlierToNegate()
187 MatchInfo = MRI.getVRegDef(Src); in matchFoldableFneg()
193 if (MRI.hasOneNonDBGUse(Src)) { in matchFoldableFneg()
194 if (allUsesHaveSourceMods(MI, MRI, 0)) in matchFoldableFneg()
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H A DAMDGPUInstructionSelector.cpp69 MRI = &MF.getRegInfo(); in setupMF()
75 const MachineRegisterInfo &MRI) const { in isVCC()
80 auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg); in isVCC()
84 const LLT Ty = MRI.getType(Reg); in isVCC()
88 return MRI.getVRegDef(Reg)->getOpcode() != AMDGPU::G_TRUNC && in isVCC()
106 if (MRI->getType(Dst.getReg()) == LLT::scalar(1)) in constrainCopyLikeIntrin()
110 = TRI.getConstrainedRegClassForOperand(Dst, *MRI); in constrainCopyLikeIntrin()
112 = TRI.getConstrainedRegClassForOperand(Src, *MRI); in constrainCopyLikeIntrin()
116 return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) && in constrainCopyLikeIntrin()
117 RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI); in constrainCopyLikeIntrin()
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/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp52 MachineRegisterInfo &MRI) { in IsRegInClass()
54 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
62 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSReg()
63 return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI); in IsVSReg()
66 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVRReg()
67 return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI); in IsVRReg()
70 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) { in IsF8Reg()
71 return IsRegInClass(Reg, &PPC::F8RCRegClass, MRI); in IsF8Reg()
74 bool IsVSFReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSFReg()
75 return IsRegInClass(Reg, &PPC::VSFRCRegClass, MRI); in IsVSFReg()
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/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp43 Register llvm::constrainRegToClass(MachineRegisterInfo &MRI, in constrainRegToClass() argument
47 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) in constrainRegToClass()
48 return MRI.createVirtualRegister(&RegClass); in constrainRegToClass()
55 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass() argument
66 auto *OldRegClass = MRI.getRegClassOrNull(Reg); in constrainOperandRegClass()
67 Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); in constrainOperandRegClass()
92 } else if (OldRegClass != MRI.getRegClassOrNull(Reg)) { in constrainOperandRegClass()
95 MachineInstr *RegDef = MRI.getVRegDef(Reg); in constrainOperandRegClass()
98 Observer->changingAllUsesOfReg(MRI, Reg); in constrainOperandRegClass()
107 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass() argument
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H A DCombinerHelper.cpp55 : Builder(B), MRI(Builder.getMF().getRegInfo()), Observer(Observer), KB(KB), in CombinerHelper()
78 auto &MRI = *MIB.getMRI(); in buildLogBase2() local
79 LLT Ty = MRI.getType(V); in buildLogBase2()
159 void CombinerHelper::replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, in replaceRegWith() argument
161 Observer.changingAllUsesOfReg(MRI, FromReg); in replaceRegWith()
163 if (MRI.constrainRegAttrs(ToReg, FromReg)) in replaceRegWith()
164 MRI.replaceRegWith(FromReg, ToReg); in replaceRegWith()
171 void CombinerHelper::replaceRegOpWith(MachineRegisterInfo &MRI, in replaceRegOpWith() argument
192 return RBI->getRegBank(Reg, MRI, *TRI); in getRegBank()
197 MRI.setRegBank(Reg, *RegBank); in setRegBank()
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/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h89 Register constrainRegToClass(MachineRegisterInfo &MRI,
104 MachineRegisterInfo &MRI,
123 MachineRegisterInfo &MRI,
145 bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI);
149 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
170 const MachineRegisterInfo &MRI);
174 const MachineRegisterInfo &MRI);
187 const MachineRegisterInfo &MRI,
193 Register VReg, const MachineRegisterInfo &MRI,
205 const MachineRegisterInfo &MRI,
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H A DMIPatternMatch.h25 [[nodiscard]] bool mi_match(Reg R, const MachineRegisterInfo &MRI, in mi_match() argument
27 return P.match(MRI, R); in mi_match()
31 [[nodiscard]] bool mi_match(MachineInstr &MI, const MachineRegisterInfo &MRI, in mi_match() argument
33 return P.match(MRI, &MI); in mi_match()
41 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
42 return MRI.hasOneUse(Reg) && SubPat.match(MRI, Reg); in match()
55 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
56 return MRI.hasOneNonDBGUse(Reg) && SubPat.match(MRI, Reg); in match()
71 const MachineRegisterInfo &MRI) { in matchConstant() argument
72 return getIConstantVRegVal(Reg, MRI); in matchConstant()
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H A DLegalizationArtifactCombiner.h35 MachineRegisterInfo &MRI; variable
51 LegalizationArtifactCombiner(MachineIRBuilder &B, MachineRegisterInfo &MRI, in LegalizationArtifactCombiner() argument
53 : Builder(B), MRI(MRI), LI(LI) {} in LegalizationArtifactCombiner()
68 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) { in tryCombineAnyExt()
70 if (MRI.getType(DstReg) == MRI.getType(TruncSrc)) in tryCombineAnyExt()
71 replaceRegOrBuildCopy(DstReg, TruncSrc, MRI, Builder, UpdatedDefs, in tryCombineAnyExt()
76 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineAnyExt()
83 if (mi_match(SrcReg, MRI, in tryCombineAnyExt()
94 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineAnyExt()
96 const LLT DstTy = MRI.getType(DstReg); in tryCombineAnyExt()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp66 MachineRegisterInfo *MRI; member in __anonc564d7130111::AArch64AdvSIMDScalar
105 const MachineRegisterInfo *MRI) { in isGPR64() argument
109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
114 const MachineRegisterInfo *MRI) { in isFPR64() argument
116 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
118 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
128 const MachineRegisterInfo *MRI, in getSrcFromCopy() argument
145 MRI) && in getSrcFromCopy()
146 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
149 MRI) && in getSrcFromCopy()
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H A DAArch64Combine.td17 [{ return matchFConstantToConstant(*${root}, MRI); }]),
24 [{ return matchICmpRedundantTrunc(*${root}, MRI, Helper.getKnownBits(), ${matchinfo}); }]),
25 (apply [{ applyICmpRedundantTrunc(*${root}, MRI, B, Observer, ${matchinfo}); }])>;
32 [{ return matchFoldGlobalOffset(*${root}, MRI, ${matchinfo}); }]),
33 (apply [{ return applyFoldGlobalOffset(*${root}, MRI, B, Observer, ${matchinfo});}])
60 [{ return matchREV(*${root}, MRI, ${matchinfo}); }]),
67 [{ return matchZip(*${root}, MRI, ${matchinfo}); }]),
74 [{ return matchUZP(*${root}, MRI, ${matchinfo}); }]),
81 [{ return matchDup(*${root}, MRI, ${matchinfo}); }]),
88 [{ return matchTRN(*${root}, MRI, ${matchinfo}); }]),
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/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp77 bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
79 bool selectFrameIndexOrGep(MachineInstr &I, MachineRegisterInfo &MRI,
81 bool selectGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI,
83 bool selectConstant(MachineInstr &I, MachineRegisterInfo &MRI,
85 bool selectTruncOrPtrToInt(MachineInstr &I, MachineRegisterInfo &MRI,
87 bool selectZext(MachineInstr &I, MachineRegisterInfo &MRI,
89 bool selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI,
91 bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
93 bool selectFCmp(MachineInstr &I, MachineRegisterInfo &MRI,
95 bool selectUadde(MachineInstr &I, MachineRegisterInfo &MRI,
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp108 bool earlySelectSHL(MachineInstr &I, MachineRegisterInfo &MRI);
112 MachineRegisterInfo &MRI);
114 bool convertPtrAddToAdd(MachineInstr &I, MachineRegisterInfo &MRI);
117 MachineRegisterInfo &MRI) const;
119 MachineRegisterInfo &MRI) const;
135 MachineRegisterInfo &MRI);
137 bool selectVectorAshrLshr(MachineInstr &I, MachineRegisterInfo &MRI);
138 bool selectVectorSHL(MachineInstr &I, MachineRegisterInfo &MRI);
165 MachineRegisterInfo &MRI);
167 bool selectInsertElt(MachineInstr &I, MachineRegisterInfo &MRI);
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H A DAArch64PostLegalizerCombiner.cpp54 MachineInstr &MI, MachineRegisterInfo &MRI, in matchExtractVecEltPairwiseAdd() argument
58 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); in matchExtractVecEltPairwiseAdd()
60 auto Cst = getIConstantVRegValWithLookThrough(Src2, MRI); in matchExtractVecEltPairwiseAdd()
66 auto *FAddMI = getOpcodeDef(TargetOpcode::G_FADD, Src1, MRI); in matchExtractVecEltPairwiseAdd()
78 getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op2, MRI); in matchExtractVecEltPairwiseAdd()
79 MachineInstr *Other = MRI.getVRegDef(Src1Op1); in matchExtractVecEltPairwiseAdd()
81 Shuffle = getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op1, MRI); in matchExtractVecEltPairwiseAdd()
82 Other = MRI.getVRegDef(Src1Op2); in matchExtractVecEltPairwiseAdd()
87 Other == MRI.getVRegDef(Shuffle->getOperand(1).getReg())) { in matchExtractVecEltPairwiseAdd()
97 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, in applyExtractVecEltPairwiseAdd() argument
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H A DAArch64PostLegalizerLowering.cpp222 static bool matchREV(MachineInstr &MI, MachineRegisterInfo &MRI, in matchREV() argument
228 LLT Ty = MRI.getType(Dst); in matchREV()
251 static bool matchTRN(MachineInstr &MI, MachineRegisterInfo &MRI, in matchTRN() argument
257 unsigned NumElts = MRI.getType(Dst).getNumElements(); in matchTRN()
272 static bool matchUZP(MachineInstr &MI, MachineRegisterInfo &MRI, in matchUZP() argument
278 unsigned NumElts = MRI.getType(Dst).getNumElements(); in matchUZP()
288 static bool matchZip(MachineInstr &MI, MachineRegisterInfo &MRI, in matchZip() argument
294 unsigned NumElts = MRI.getType(Dst).getNumElements(); in matchZip()
306 MachineRegisterInfo &MRI, in matchDupFromInsertVectorElt() argument
326 MI.getOperand(1).getReg(), MRI); in matchDupFromInsertVectorElt()
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H A DAArch64PreLegalizerCombiner.cpp39 MachineRegisterInfo &MRI) { in matchFConstantToConstant() argument
42 const unsigned DstSize = MRI.getType(DstReg).getSizeInBits(); in matchFConstantToConstant()
49 return all_of(MRI.use_nodbg_instructions(DstReg), in matchFConstantToConstant()
65 static bool matchICmpRedundantTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, in matchICmpRedundantTrunc() argument
74 LLT LHSTy = MRI.getType(LHS); in matchICmpRedundantTrunc()
81 if (!mi_match(LHS, MRI, m_GTrunc(m_Reg(WideReg))) || in matchICmpRedundantTrunc()
82 !mi_match(RHS, MRI, m_SpecificICst(0))) in matchICmpRedundantTrunc()
85 LLT WideTy = MRI.getType(WideReg); in matchICmpRedundantTrunc()
94 static bool applyICmpRedundantTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, in applyICmpRedundantTrunc() argument
100 LLT WideTy = MRI.getType(WideReg); in applyICmpRedundantTrunc()
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H A DAArch64RegisterBankInfo.cpp293 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrAlternativeMappings() local
299 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
320 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
356 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
446 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getSameKindOfOperandsMapping() local
452 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getSameKindOfOperandsMapping()
468 LLT OpTy = MRI.getType(MI.getOperand(Idx).getReg()); in getSameKindOfOperandsMapping()
496 const MachineRegisterInfo &MRI, in hasFPConstraints() argument
514 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
529 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1); in hasFPConstraints()
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/openbsd-src/gnu/llvm/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp64 void processCandidate(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
67 void processDstReg(MachineRegisterInfo *MRI, Register &DstReg,
70 void processInst(MachineRegisterInfo *MRI, MachineInstr *Inst,
72 void checkADDrr(MachineRegisterInfo *MRI, MachineOperand *RelocOp,
74 void checkShift(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
102 void BPFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI, in checkADDrr() argument
112 llvm::make_early_inc_range(MRI->use_operands(Op0.getReg()))) { in checkADDrr()
114 if (!MRI->getUniqueVRegDef(MO.getReg())) in checkADDrr()
154 void BPFMISimplifyPatchable::checkShift(MachineRegisterInfo *MRI, in checkShift() argument
168 void BPFMISimplifyPatchable::processCandidate(MachineRegisterInfo *MRI, in processCandidate() argument
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/openbsd-src/gnu/llvm/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp42 MachineRegisterInfo &MRI = MF.getRegInfo(); in addConstantsToTrack() local
64 auto *BuildVec = MRI.getVRegDef(MI.getOperand(2).getReg()); in addConstantsToTrack()
77 MachineInstr *SrcMI = MRI.getVRegDef(MI.getOperand(2).getReg()); in addConstantsToTrack()
88 MRI.replaceRegWith(MI->getOperand(0).getReg(), Reg); in addConstantsToTrack()
97 MachineRegisterInfo &MRI = MF.getRegInfo(); in foldConstantsIntoIntrinsics() local
106 MachineInstr *ConstMI = MRI.getVRegDef(MOp.getReg()); in foldConstantsIntoIntrinsics()
111 if (MRI.use_empty(ConstMI->getOperand(0).getReg())) in foldConstantsIntoIntrinsics()
146 MachineRegisterInfo &MRI, in propagateSPIRVType() argument
172 MachineInstr *Def = Op.isReg() ? MRI.getVRegDef(Op.getReg()) : nullptr; in propagateSPIRVType()
174 SpirvTy = propagateSPIRVType(Def, GR, MRI, MIB); in propagateSPIRVType()
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/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp48 MachineRegisterInfo &MRI) const;
60 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
66 bool validOpRegPair(MachineRegisterInfo &MRI, unsigned LHS, unsigned RHS,
70 bool validReg(MachineRegisterInfo &MRI, unsigned Reg, unsigned ExpectedSize,
186 MachineRegisterInfo &MRI, in guessRegClass() argument
189 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
192 const unsigned Size = MRI.getType(Reg).getSizeInBits(); in guessRegClass()
212 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, in selectCopy() argument
218 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI); in selectCopy()
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