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/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstrMMX.td1 //===-- X86InstrMMX.td - Describe the MMX Instruction Set --*- tablegen -*-===//
9 // This file describes the X86 MMX instruction set, defining the instructions,
13 // All instructions that use MMX should be in this file, even if they also use
19 // MMX Multiclasses
33 // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic.
73 /// Unary MMX instructions requiring SSSE3.
87 /// Binary MMX instructions requiring SSSE3.
107 /// PALIGN MMX instructions (require SSSE3).
148 // MMX EMMS Instruction
157 // MMX Scalar Instructions
[all …]
H A DX86Instr3DNow.td9 // This file describes the 3DNow! instruction set, which extends MMX to support
56 defm PAVGUSB : I3DNow_binop_rm_int<0xBF, "pavgusb", SchedWriteVecALU.MMX, 1>;
74 defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw", SchedWriteVecIMul.MMX, 1>;
112 defm PSWAPD : I3DNow_conv_rm_int<0xBB, "pswapd", SchedWriteShuffle.MMX, "a">;
H A DX86InstrFormats.td570 // MMXPI - SSE 1 & 2 packed instructions with MMX operands
638 // MMX operands.
640 // MMX operands.
712 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.
713 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.
716 // uses the MMX registers. The 64-bit versions are grouped with the MMX
995 // MMX Instruction templates
998 // MMXI - MMX instructions with TB prefix.
999 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
1000 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
[all …]
H A DX86Subtarget.h58 NoThreeDNow, MMX, ThreeDNow, ThreeDNowA enumerator
211 bool hasMMX() const { return X863DNowLevel >= MMX; } in hasMMX()
H A DX86CallingConv.td140 // MMX type gets 8 byte slot in stack , while alignment depends on target
258 // MMX vector types are always returned in MM0. If the target doesn't have
348 // MMX vector types are always returned in XMM0.
417 // MMX vector types are returned in XMM0, XMM1, XMM2 and XMM3.
550 // The first 8 MMX vector arguments are passed in XMM registers on Darwin.
661 // The first 4 MMX vector arguments are passed in GPRs.
H A DX86Schedule.td83 X86FoldableSchedWrite MMX = sScl; // MMX operations.
119 X86SchedWriteMoveLS MMX = sScl; // MMX operations.
H A DX86ScheduleBtVer2.td58 // The PRF in the floating point unit can eliminate a move from a MMX or SSE
976 // MMX Zero-idioms.
1019 // MMX
1040 // MMX variants.
H A DX86InstrFragmentsSIMD.td14 // MMX specific DAG Nodes.
17 // Low word of MMX to GPR.
20 // GPR to low word of MMX.
25 // MMX Pattern Fragments
H A DX86ScheduleZnver1.td890 //=== Integer MMX and XMM Instructions ===//
1337 // MMX Zero-idioms.
1384 // MMX
H A DX86ScheduleZnver2.td900 //=== Integer MMX and XMM Instructions ===//
1338 // MMX Zero-idioms.
1385 // MMX
/openbsd-src/gnu/gcc/gcc/config/i386/
H A Di386.opt133 Target Report Mask(MMX)
134 Support MMX built-in functions
190 Support MMX and SSE built-in functions and code generation
194 Support MMX, SSE and SSE2 built-in functions and code generation
198 Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
H A Dpentium.md33 ;; The non-MMX Pentium slots an instruction with prefixes on U pipe only,
34 ;; while MMX Pentium can slot it on either U or V. Model non-MMX Pentium
35 ;; rules, because it results in noticeably better code on non-MMX Pentium
36 ;; and doesn't hurt much on MMX. (Prefixed instructions are not very
H A Dmmx.md1 ;; GCC machine description for MMX and 3dNOW! instructions
22 ;; The MMX and 3dNOW! patterns are in the same file because they use
24 ;; the base integer MMX isa.
34 ;; 8 byte integral modes handled by MMX (and by extension, SSE)
37 ;; All 8-byte vector modes handled by MMX
53 ;; All of these patterns are enabled for MMX as well as 3dNOW.
H A Dppro.md109 ;; AGU MMX
110 ;; MMX P3FPU
447 ;; MMX instructions can execute on either port 0 or port 1 with a
454 ;; MMX instructions are either of the type reg-reg, or read-modify, and
733 ;; the ALU units, and the MMX units.
H A Dconstraints.md81 "Any MMX register.")
H A Dk6.md45 ;; with the Integer X unit. This unit is used for MMX,
/openbsd-src/gnu/usr.bin/gcc/gcc/config/i386/
H A Dpentium.md33 ;; The non-MMX Pentium slots an instruction with prefixes on U pipe only,
34 ;; while MMX Pentium can slot it on either U or V. Model non-MMX Pentium
35 ;; rules, because it results in noticeably better code on non-MMX Pentium
36 ;; and doesn't hurt much on MMX. (Prefixed instructions are not very
/openbsd-src/usr.bin/file/magdir/
H A Dscientific56 1028 string MMX\000\000\000\000\000\000\000\000\000\000\000\000\000 MAR Area Detector Image,
/openbsd-src/gnu/usr.bin/binutils/gas/doc/
H A Dc-i386.texi32 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
293 These registers are overloaded by 8 MMX registers @samp{%mm0},
585 @section Intel's MMX and AMD's 3DNow! SIMD Operations
587 @cindex MMX, i386
590 @cindex MMX, x86-64
594 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
595 instructions for integer data), available on Intel's Pentium MMX
604 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
607 floating point values. The MMX registers cannot be used at the same time
/openbsd-src/gnu/usr.bin/binutils-2.17/gas/doc/
H A Dc-i386.texi33 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
303 These registers are overloaded by 8 MMX registers @samp{%mm0},
595 @section Intel's MMX and AMD's 3DNow! SIMD Operations
597 @cindex MMX, i386
600 @cindex MMX, x86-64
604 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
605 instructions for integer data), available on Intel's Pentium MMX
614 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
617 floating point values. The MMX registers cannot be used at the same time
/openbsd-src/gnu/llvm/llvm/include/llvm/IR/
H A DIntrinsics.h114 MMX, enumerator
/openbsd-src/gnu/llvm/clang/lib/Basic/Targets/
H A DX86.cpp384 .Case("+mmx", MMX) in handleTargetFeatures()
892 case MMX: in getTargetDefines()
1071 .Case("mmx", MMX3DNowLevel >= MMX) in hasFeature()
/openbsd-src/gnu/usr.bin/binutils-2.17/include/opcode/
H A DChangeLog348 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
349 available only with SSE2. Change the MMX additions introduced by SSE
/openbsd-src/gnu/llvm/llvm/include/llvm/TargetParser/
H A DX86TargetParser.def127 X86_FEATURE_COMPAT(MMX, "mmx", 1)
/openbsd-src/gnu/llvm/llvm/lib/IR/
H A DFunction.cpp1106 OutputTable.push_back(IITDescriptor::get(IITDescriptor::MMX, 0)); in DecodeIITType()
1375 case IITDescriptor::MMX: return Type::getX86_MMXTy(Context); in DecodeFixedType()
1548 case IITDescriptor::MMX: return !Ty->isX86_MMXTy(); in matchIntrinsicType()

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