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Searched refs:LS1 (Results 1 – 6 of 6) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonConstPropagation.cpp1109 LatticeCell LS1, LS2; in evaluateCMPrr() local
1110 if (!getCell(R1, Inputs, LS1) || !getCell(R2, Inputs, LS2)) in evaluateCMPrr()
1113 bool IsProp1 = LS1.isProperty(); in evaluateCMPrr()
1116 uint32_t Prop1 = LS1.properties(); in evaluateCMPrr()
1413 LatticeCell LS1; in evaluateANDri() local
1414 if (!getCell(R1, Inputs, LS1)) in evaluateANDri()
1416 if (LS1.isBottom() || LS1.isProperty()) in evaluateANDri()
1420 for (unsigned i = 0; i < LS1.size(); ++i) { in evaluateANDri()
1421 bool Eval = constToInt(LS1.Values[i], A) && in evaluateANDri()
1480 LatticeCell LS1; in evaluateORri() local
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/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX3T110.td291 // 1 cycle on LS0/LS1.
297 // 2 cycles on LS0/LS1.
303 // 4 cycles on LS0/LS1.
310 // 5 cycles on LS0/LS1.
316 // 6 cycles on LS0/LS1.
322 // 4 + 5 cycles on LS0/LS1.
332 // 4 + 8 cycles on LS0/LS1.
342 // 11 cycles on LS0/LS1 and I1.
349 // 1 cycles on LS0/LS1 and I0/I1/I2/I3.
356 // 1 cycles on LS0/LS1 and 2 of I0/I1/I2/I3.
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H A DAArch64SchedThunderX2T99.td213 // 1 cycles on LS0 or LS1.
218 // 1 cycles on LS0 or LS1 and I0, I1, or I2.
224 // 1 cycles on LS0 or LS1 and 2 of I0, I1, or I2.
231 // 2 cycles on LS0 or LS1.
237 // 4 cycles on LS0 or LS1.
243 // 5 cycles on LS0 or LS1.
249 // 6 cycles on LS0 or LS1.
255 // 4 cycles on LS0 or LS1 and I0, I1, or I2.
261 // 4 cycles on LS0 or LS1 and 2 of I0, I1, or I2.
268 // 5 cycles on LS0 or LS1 and I0, I1, or I2.
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/openbsd-src/gnu/gcc/gcc/config/mips/
H A Dsb1.md146 ;; Indexed loads can only execute on LS1 pipe.
182 ;; Indexed stores can only execute on LS1 pipe.
208 ;; On SB-1, simple alu instructions can execute on the LS1 unit.
229 ;; insns to the LS unit, and that we don't conflict with insns that need LS1
231 ;; alu instructions that are not supposed to be scheduled to LS1 don't
232 ;; accidentally end up there because LS1 is free when they are issued. This
242 ;; On SB-1A, simple alu instructions can not execute on the LS1 unit, and we
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp2479 GLoadStore *LS1 = dyn_cast<GLoadStore>(I1); in matchEqualDefs() local
2481 if (!LS1 || !LS2) in matchEqualDefs()
2485 (LS1->getMemSizeInBits() != LS2->getMemSizeInBits())) in matchEqualDefs()
/openbsd-src/gnu/usr.bin/gcc/gcc/config/mips/
H A Dmips.md9888 ;; bal $LS1
9890 ;; $LS1:
9892 ;; lw $reg,$L1-$LS1($reg)
9896 ;; .word case1-$LS1
9897 ;; .word case2-$LS1