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Searched refs:IsLE (Results 1 – 20 of 20) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Object/
H A DDecompressor.cpp21 bool IsLE, bool Is64Bit) { in create() argument
23 if (Error Err = D.consumeCompressedHeader(Is64Bit, IsLE)) in create()
/openbsd-src/gnu/llvm/llvm/include/llvm/Object/
H A DDecompressor.h29 bool IsLE, bool Is64Bit);
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td3620 def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>;
3621 def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>;
3622 def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>;
3623 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
3624 def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>;
3625 def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>;
3627 def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>;
3628 def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>;
3629 def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>;
3630 def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>;
[all …]
H A DMipsInstrInfo.td236 def IsLE : Predicate<"Subtarget->isLittle()">;
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h647 bool &Swap, bool IsLE);
668 bool &Swap, bool IsLE);
688 unsigned &InsertAtByte, bool &Swap, bool IsLE);
H A DPPCISelLowering.cpp1835 bool IsLE = DAG.getDataLayout().isLittleEndian(); in isVPKUHUMShuffleMask() local
1837 if (IsLE) in isVPKUHUMShuffleMask()
1843 if (!IsLE) in isVPKUHUMShuffleMask()
1849 unsigned j = IsLE ? 0 : 1; in isVPKUHUMShuffleMask()
1866 bool IsLE = DAG.getDataLayout().isLittleEndian(); in isVPKUWUMShuffleMask() local
1868 if (IsLE) in isVPKUWUMShuffleMask()
1875 if (!IsLE) in isVPKUWUMShuffleMask()
1882 unsigned j = IsLE ? 0 : 2; in isVPKUWUMShuffleMask()
1907 bool IsLE = DAG.getDataLayout().isLittleEndian(); in isVPKUDUMShuffleMask() local
1909 if (IsLE) in isVPKUDUMShuffleMask()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/ObjectYAML/
H A DMachOEmitter.cpp377 makeRelocationInfo(const MachOYAML::Relocation &R, bool IsLE) { in makeRelocationInfo() argument
381 if (IsLE) in makeRelocationInfo()
H A DELFEmitter.cpp1989 bool IsLE = Doc.Header.Data == ELFYAML::ELF_ELFDATA(ELF::ELFDATA2LSB); in yaml2elf() local
1992 if (IsLE) in yaml2elf()
1996 if (IsLE) in yaml2elf()
/openbsd-src/gnu/llvm/llvm/lib/DWP/
H A DDWP.cpp291 bool IsLE = isa<object::ELF32LEObjectFile>(Obj) || in handleCompressedSection() local
295 Expected<Decompressor> Dec = Decompressor::create(Name, Contents, IsLE, Is64); in handleCompressedSection()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMPredicates.td220 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">;
H A DARMInstrThumb.td1635 Requires<[IsThumb, IsThumb1Only, IsLE]>;
1637 Requires<[IsThumb, IsThumb1Only, IsLE]>;
1639 Requires<[IsThumb, IsThumb1Only, IsLE]>;
H A DARMInstrNEON.td2462 let Predicates = [IsLE,HasNEON] in {
2487 let Predicates = [IsLE,HasNEON] in {
7530 let Predicates = [IsLE,HasNEON] in {
8024 let Predicates = [HasNEON,IsLE] in {
8049 let Predicates = [HasNEON,IsLE] in {
H A DARMInstrMVE.td7290 let Predicates = [HasMVEInt, IsLE] in {
7449 let Predicates = [IsLE,HasMVEInt] in {
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td249 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
2826 let Predicates = [IsLE] in {
2840 let Predicates = [IsLE] in {
2972 let Predicates = [IsLE] in {
2993 let Predicates = [IsLE] in {
3161 let Predicates = [IsLE] in {
3179 let Predicates = [IsLE] in {
3502 let Predicates = [IsLE] in {
3516 let Predicates = [IsLE, UseSTRQro] in {
3601 let Predicates = [IsLE] in {
[all …]
H A DAArch64SVEInstrInfo.td2455 let Predicates = [IsLE] in {
2756 let Predicates = [IsLE] in {
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp665 bool IsLE = DAG.getDataLayout().isLittleEndian(); in SimplifyMultipleUseDemandedBits() local
693 unsigned EltOffset = IsLE ? i : (Scale - 1 - i); in SimplifyMultipleUseDemandedBits()
710 if (IsLE && (NumSrcEltBits % NumDstEltBits) == 0) { in SimplifyMultipleUseDemandedBits()
827 if (IsLE && DemandedElts == 1 && in SimplifyMultipleUseDemandedBits()
1076 bool IsLE = TLO.DAG.getDataLayout().isLittleEndian(); in SimplifyDemandedBits() local
2248 if (IsLE && IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()
2288 if (IsLE && IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()
2341 if (IsLE && IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()
2513 unsigned EltOffset = IsLE ? i : (Scale - 1 - i); in SimplifyDemandedBits()
2533 } else if (IsLE && (NumSrcEltBits % BitWidth) == 0) { in SimplifyDemandedBits()
[all …]
H A DSelectionDAG.cpp3136 bool IsLE = getDataLayout().isLittleEndian(); in computeKnownBits() local
3155 unsigned Shifts = IsLE ? i : SubScale - 1 - i; in computeKnownBits()
3175 unsigned Shifts = IsLE ? i : NumElts - 1 - i; in computeKnownBits()
4096 bool IsLE = getDataLayout().isLittleEndian(); in ComputeNumSignBits() local
4116 SubOffset = (IsLE ? ((Scale - 1) - SubOffset) : SubOffset); in ComputeNumSignBits()
5843 bool IsLE = getDataLayout().isLittleEndian(); in FoldConstantArithmetic() local
5847 if (BV1->getConstantRawBits(IsLE, EltBits, RawBits1, UndefElts1) && in FoldConstantArithmetic()
5848 BV2->getConstantRawBits(IsLE, EltBits, RawBits2, UndefElts2)) { in FoldConstantArithmetic()
5862 BuildVectorSDNode::recastRawBits(IsLE, BVVT.getScalarSizeInBits(), in FoldConstantArithmetic()
H A DDAGCombiner.cpp14558 bool IsLE = DAG.getDataLayout().isLittleEndian(); in ConstantFoldBITCASTofBUILD_VECTOR() local
14559 if (!BVN->getConstantRawBits(IsLE, DstBitSize, RawBits, UndefElements)) in ConstantFoldBITCASTofBUILD_VECTOR()
18652 bool IsLE = DAG.getDataLayout().isLittleEndian(); in mergeStoresOfConstantsOrVecElts() local
18654 unsigned Idx = IsLE ? (NumStores - 1 - i) : i; in mergeStoresOfConstantsOrVecElts()
20742 bool IsLE = DAG.getDataLayout().isLittleEndian(); in visitEXTRACT_VECTOR_ELT() local
20745 unsigned BCTruncElt = IsLE ? 0 : NumElts - 1; in visitEXTRACT_VECTOR_ELT()
20759 BCTruncElt = IsLE ? 0 : XBitWidth / VecEltBitWidth - 1; in visitEXTRACT_VECTOR_ELT()
/openbsd-src/gnu/llvm/clang/lib/CodeGen/
H A DCGBuiltin.cpp15749 bool IsLE = getTarget().isLittleEndian(); in EmitPPCBuiltinExpr() local
15756 if (!IsLE) in EmitPPCBuiltinExpr()
15767 llvm::Function *Lvs = CGM.getIntrinsic(IsLE ? Intrinsic::ppc_altivec_lvsr in EmitPPCBuiltinExpr()
15776 Op0 = IsLE ? HiLd : LoLd; in EmitPPCBuiltinExpr()
15777 Op1 = IsLE ? LoLd : HiLd; in EmitPPCBuiltinExpr()
15779 Constant *Zero = llvm::Constant::getNullValue(IsLE ? ResTy : AllElts->getType()); in EmitPPCBuiltinExpr()
15781 if (IsLE) { in EmitPPCBuiltinExpr()
15803 bool IsLE = getTarget().isLittleEndian(); in EmitPPCBuiltinExpr() local
15810 if (IsLE) { in EmitPPCBuiltinExpr()
15847 if (IsLE && Width > 1) { in EmitPPCBuiltinExpr()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp7759 bool IsLE = SI.getModule()->getDataLayout().isLittleEndian(); in splitMergedValStore() local
7766 const bool IsOffsetStore = (IsLE && Upper) || (!IsLE && !Upper); in splitMergedValStore()