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Searched refs:IsAGPR (Results 1 – 6 of 6) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUResourceUsageAnalysis.cpp262 bool IsAGPR = false; in analyzeResourceUsage() local
356 IsAGPR = true; in analyzeResourceUsage()
368 IsAGPR = true; in analyzeResourceUsage()
378 IsAGPR = true; in analyzeResourceUsage()
390 IsAGPR = true; in analyzeResourceUsage()
400 IsAGPR = true; in analyzeResourceUsage()
410 IsAGPR = true; in analyzeResourceUsage()
420 IsAGPR = true; in analyzeResourceUsage()
432 IsAGPR = true; in analyzeResourceUsage()
442 IsAGPR = true; in analyzeResourceUsage()
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H A DSIRegisterInfo.cpp1328 const bool IsAGPR = !ST.hasGFX90AInsts() && isAGPRClass(RC); in buildSpillLoadStore() local
1333 unsigned EltSize = (IsFlat && !IsAGPR) ? std::min(RegWidth, 16u) : 4u; in buildSpillLoadStore()
1590 if (IsAGPR) { in buildSpillLoadStore()
1627 MIB.addReg(TmpOffsetVGPR, getKillRegState(IsLastSubReg && !IsAGPR)); in buildSpillLoadStore()
1651 if (!IsAGPR && NeedSuperRegDef) in buildSpillLoadStore()
1654 if (!IsStore && IsAGPR && TmpIntermediateVGPR != AMDGPU::NoRegister) { in buildSpillLoadStore()
H A DSILoadStoreOptimizer.cpp118 bool IsAGPR; member
714 IsAGPR = LSO.TRI->hasAGPRs(LSO.getDataRegClass(*MI)); in setMI()
2220 AddrList.front().IsAGPR == CI.IsAGPR && in addInstToMergeableList()
2276 if (CI.InstClass == DS_WRITE && CI.IsAGPR) { in collectMergeableInsts()
H A DSIFixSGPRCopies.cpp303 bool IsAGPR = TRI->isAGPRClass(DstRC); in foldVGPRCopyIntoRegSequence() local
318 if (IsAGPR) { in foldVGPRCopyIntoRegSequence()
H A DSIInstrInfo.cpp5143 bool IsAGPR = RI.isAGPR(MRI, MO->getReg()); in isOperandLegal() local
5144 if (IsAGPR && !ST.hasMAIInsts()) in isOperandLegal()
5147 if (IsAGPR && in isOperandLegal()
5157 RI.isAGPR(MRI, MI.getOperand(DataIdx).getReg()) != IsAGPR) in isOperandLegal()
5161 RI.isAGPR(MRI, MI.getOperand(VDstIdx).getReg()) != IsAGPR) in isOperandLegal()
5167 RI.isAGPR(MRI, MI.getOperand(Data1Idx).getReg()) != IsAGPR) in isOperandLegal()
8727 bool IsAGPR = RI.isAGPR(MRI, DataReg); in enforceOperandRCAlignment() local
8729 IsAGPR ? &AMDGPU::AGPR_32RegClass : &AMDGPU::VGPR_32RegClass); in enforceOperandRCAlignment()
8732 MRI.createVirtualRegister(IsAGPR ? &AMDGPU::AReg_64_Align2RegClass in enforceOperandRCAlignment()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp1620 bool IsAGPR = Val & 512; in decodeSrcOp() local
1624 return createRegOperand(IsAGPR ? getAgprClassId(Width) in decodeSrcOp()