| /openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | ValueTypes.h | 400 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in getHalfSizedIntegerVT() local 401 IntVT <= MVT::LAST_INTEGER_VALUETYPE; ++IntVT) { in getHalfSizedIntegerVT() 402 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT()
|
| H A D | TargetLowering.h | 2263 virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, in shouldUseStrictFP_TO_INT() argument
|
| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 434 EVT IntVT = ValueVTs[0]; in ComputePHILiveOutRegInfo() local 436 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1) in ComputePHILiveOutRegInfo() 438 IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT); in ComputePHILiveOutRegInfo() 439 unsigned BitWidth = IntVT.getSizeInBits(); in ComputePHILiveOutRegInfo()
|
| H A D | FastISel.cpp | 301 EVT IntVT = TLI.getPointerTy(DL); in materializeConstant() local 302 uint32_t IntBitWidth = IntVT.getSizeInBits(); in materializeConstant() 310 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeConstant() 1619 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); in selectFNeg() local 1620 if (!TLI.isTypeLegal(IntVT)) in selectFNeg() 1623 Register IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), in selectFNeg() 1629 IntVT.getSimpleVT(), ISD::XOR, IntReg, in selectFNeg() 1630 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT()); in selectFNeg() 1634 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST, in selectFNeg()
|
| H A D | TargetLowering.cpp | 7731 EVT IntVT = SrcVT.changeTypeToInteger(); in expandFP_TO_SINT() local 7732 EVT IntShVT = getShiftAmountTy(IntVT, DAG.getDataLayout()); in expandFP_TO_SINT() 7734 SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT); in expandFP_TO_SINT() 7735 SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT); in expandFP_TO_SINT() 7736 SDValue Bias = DAG.getConstant(127, dl, IntVT); in expandFP_TO_SINT() 7737 SDValue SignMask = DAG.getConstant(APInt::getSignMask(SrcEltBits), dl, IntVT); in expandFP_TO_SINT() 7738 SDValue SignLowBit = DAG.getConstant(SrcEltBits - 1, dl, IntVT); in expandFP_TO_SINT() 7739 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT); in expandFP_TO_SINT() 7741 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Src); in expandFP_TO_SINT() 7744 ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), in expandFP_TO_SINT() [all …]
|
| H A D | LegalizeDAG.cpp | 1606 EVT IntVT = SignAsInt.IntValue.getValueType(); in ExpandFCOPYSIGN() local 1607 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT); in ExpandFCOPYSIGN() 1608 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue, in ExpandFCOPYSIGN() 1617 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit, in ExpandFCOPYSIGN() 1618 DAG.getConstant(0, DL, IntVT), ISD::SETNE); in ExpandFCOPYSIGN() 1632 EVT ShiftVT = IntVT; in ExpandFCOPYSIGN() 1660 EVT IntVT = SignAsInt.IntValue.getValueType(); in ExpandFNEG() local 1663 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT); in ExpandFNEG() 1665 DAG.getNode(ISD::XOR, DL, IntVT, SignAsInt.IntValue, SignMask); in ExpandFNEG() 1685 EVT IntVT = ValueAsInt.IntValue.getValueType(); in ExpandFABS() local [all …]
|
| H A D | LegalizeFloatTypes.cpp | 951 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in findFPToIntLibcall() local 952 IntVT <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; in findFPToIntLibcall() 953 ++IntVT) { in findFPToIntLibcall() 954 Promoted = (MVT::SimpleValueType)IntVT; in findFPToIntLibcall()
|
| H A D | DAGCombiner.cpp | 14533 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); in ConstantFoldBITCASTofBUILD_VECTOR() local 14534 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); in ConstantFoldBITCASTofBUILD_VECTOR() 14535 SrcEltVT = IntVT; in ConstantFoldBITCASTofBUILD_VECTOR() 18406 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VTSize.getFixedValue()); in TransformFPLoadStorePair() local 18407 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || in TransformFPLoadStorePair() 18408 !TLI.isOperationLegal(ISD::STORE, IntVT) || in TransformFPLoadStorePair() 18411 !TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), IntVT, in TransformFPLoadStorePair() 18413 !TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), IntVT, in TransformFPLoadStorePair() 18419 DAG.getLoad(IntVT, SDLoc(Value), LD->getChain(), LD->getBasePtr(), in TransformFPLoadStorePair() 24097 EVT IntVT = VT.changeVectorElementTypeToInteger(); in visitVECTOR_SHUFFLE() local [all …]
|
| H A D | SelectionDAG.cpp | 6832 EVT IntVT = VT.getScalarType(); in getMemsetValue() local 6833 if (!IntVT.isInteger()) in getMemsetValue() 6834 IntVT = EVT::getIntegerVT(*DAG.getContext(), IntVT.getSizeInBits()); in getMemsetValue() 6836 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, IntVT, Value); in getMemsetValue() 6841 Value = DAG.getNode(ISD::MUL, dl, IntVT, Value, in getMemsetValue() 6842 DAG.getConstant(Magic, dl, IntVT)); in getMemsetValue()
|
| H A D | SelectionDAGBuilder.cpp | 242 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); in getCopyFromParts() local 243 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V, CC); in getCopyFromParts()
|
| /openbsd-src/gnu/llvm/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 162 for (MVT IntVT : {MVT::i32, MVT::i64}) { in initSPUActions() 164 setOperationAction(ISD::UREM, IntVT, Expand); in initSPUActions() 165 setOperationAction(ISD::SREM, IntVT, Expand); in initSPUActions() 166 setOperationAction(ISD::SDIVREM, IntVT, Expand); in initSPUActions() 167 setOperationAction(ISD::UDIVREM, IntVT, Expand); in initSPUActions() 170 setOperationAction(ISD::SHL_PARTS, IntVT, Expand); in initSPUActions() 171 setOperationAction(ISD::SRA_PARTS, IntVT, Expand); in initSPUActions() 172 setOperationAction(ISD::SRL_PARTS, IntVT, Expand); in initSPUActions() 176 setOperationAction(ISD::MULHU, IntVT, Expand); in initSPUActions() 177 setOperationAction(ISD::MULHS, IntVT, Expand); in initSPUActions() [all …]
|
| /openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 2132 MVT IntVT = ContainerVT.changeVectorElementTypeToInteger(); in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND() local 2150 Truncated = DAG.getNode(RISCVISD::VFCVT_RM_X_F_VL, DL, IntVT, Src, Mask, in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND() 2155 Truncated = DAG.getNode(RISCVISD::VFCVT_RTZ_X_F_VL, DL, IntVT, Src, in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND() 2159 Truncated = DAG.getNode(RISCVISD::VFCVT_X_F_VL, DL, IntVT, Src, Mask, VL); in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND() 3590 EVT IntVT = FloatVT.changeVectorElementTypeToInteger(); in lowerCTLZ_CTTZ_ZERO_UNDEF() local 3591 SDValue Bitcast = DAG.getBitcast(IntVT, FloatVal); in lowerCTLZ_CTTZ_ZERO_UNDEF() 3593 SDValue Exp = DAG.getNode(ISD::SRL, DL, IntVT, Bitcast, in lowerCTLZ_CTTZ_ZERO_UNDEF() 3594 DAG.getConstant(ShiftAmt, DL, IntVT)); in lowerCTLZ_CTTZ_ZERO_UNDEF() 3596 if (IntVT.bitsLT(VT)) in lowerCTLZ_CTTZ_ZERO_UNDEF() 3598 else if (IntVT.bitsGT(VT)) in lowerCTLZ_CTTZ_ZERO_UNDEF() [all …]
|
| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 1767 EVT IntVT = MemVT.changeTypeToInteger(); in lowerKernargMemParameter() local 1779 SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, SL, IntVT, Extract); in lowerKernargMemParameter() 4882 EVT IntVT = LoadVT.changeTypeToInteger(); in lowerIntrinsicLoad() local 4909 return getMemIntrinsicNode(Opc, DL, M->getVTList(), Ops, IntVT, in lowerIntrinsicLoad() 5784 MVT IntVT = MVT::getIntegerVT(VecSize); in lowerINSERT_VECTOR_ELT() local 5791 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT, in lowerINSERT_VECTOR_ELT() 5792 DAG.getConstant(EltMask, SL, IntVT), ScaledIdx); in lowerINSERT_VECTOR_ELT() 5795 SDValue ExtVal = DAG.getNode(ISD::BITCAST, SL, IntVT, in lowerINSERT_VECTOR_ELT() 5799 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal); in lowerINSERT_VECTOR_ELT() 5802 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec); in lowerINSERT_VECTOR_ELT() [all …]
|
| H A D | AMDGPUISelLowering.cpp | 1692 MVT IntVT = MVT::i32; in LowerDIVREM24() local 1712 SDValue jq = DAG.getConstant(1, DL, IntVT); in LowerDIVREM24() 1762 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq); in LowerDIVREM24()
|
| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 778 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits()); in initActions() local 779 if (IntVT.isValid()) { in initActions() 781 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT); in initActions()
|
| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 4056 MVT IntVT = is64Bit() ? MVT::i64 : MVT::i32; in forwardMustTailParameters() local 4057 RegParmTypes.push_back(IntVT); in forwardMustTailParameters() 21193 MVT IntVT = CastToInt.getSimpleValueType(); in lowerFPToIntToFP() local 21202 IntVT != MVT::i32) in lowerFPToIntToFP() 21206 unsigned IntSize = IntVT.getSizeInBits(); in lowerFPToIntToFP() 21209 MVT VecIntVT = MVT::getVectorVT(IntVT, 128 / IntSize); in lowerFPToIntToFP() 23932 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); in LowerVectorAllZero() local 23933 if (!DAG.getTargetLoweringInfo().isTypeLegal(IntVT)) in LowerVectorAllZero() 23936 DAG.getBitcast(IntVT, MaskBits(V)), in LowerVectorAllZero() 23937 DAG.getConstant(0, DL, IntVT)); in LowerVectorAllZero() [all …]
|
| H A D | X86ISelDAGToDAG.cpp | 1206 EVT IntVT = EVT(VecVT).changeVectorElementTypeToInteger(); in PreprocessISelDAG() local 1207 Op0 = CurDAG->getNode(ISD::BITCAST, dl, IntVT, Op0); in PreprocessISelDAG() 1208 Op1 = CurDAG->getNode(ISD::BITCAST, dl, IntVT, Op1); in PreprocessISelDAG() 1217 Res = CurDAG->getNode(Opc, dl, IntVT, Op0, Op1); in PreprocessISelDAG()
|
| /openbsd-src/gnu/llvm/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1004 MVT IntVT = MVT::i32; in LowerFormalArguments() local 1005 RegParmTypes.push_back(IntVT); in LowerFormalArguments()
|
| /openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 5522 MVT IntVT = MVT::getIntegerVT(VT.getScalarSizeInBits()); in lowerINSERT_VECTOR_ELT() local 5523 MVT IntVecVT = MVT::getVectorVT(IntVT, VT.getVectorNumElements()); in lowerINSERT_VECTOR_ELT() 5526 DAG.getNode(ISD::BITCAST, DL, IntVT, Op1), Op2); in lowerINSERT_VECTOR_ELT() 5549 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits()); in lowerEXTRACT_VECTOR_ELT() local 5550 MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements()); in lowerEXTRACT_VECTOR_ELT() 5551 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT, in lowerEXTRACT_VECTOR_ELT()
|
| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 4055 EVT IntVT = SrcVT.changeVectorElementTypeToInteger(); in LowerVectorFP_TO_INT_SAT() local 4056 SDValue NativeCvt = DAG.getNode(Op.getOpcode(), DL, IntVT, SrcVal, in LowerVectorFP_TO_INT_SAT() 4057 DAG.getValueType(IntVT.getScalarType())); in LowerVectorFP_TO_INT_SAT() 4061 APInt::getSignedMaxValue(SatWidth).sext(SrcElementWidth), DL, IntVT); in LowerVectorFP_TO_INT_SAT() 4062 SDValue Min = DAG.getNode(ISD::SMIN, DL, IntVT, NativeCvt, MinC); in LowerVectorFP_TO_INT_SAT() 4064 APInt::getSignedMinValue(SatWidth).sext(SrcElementWidth), DL, IntVT); in LowerVectorFP_TO_INT_SAT() 4065 Sat = DAG.getNode(ISD::SMAX, DL, IntVT, Min, MaxC); in LowerVectorFP_TO_INT_SAT() 4068 APInt::getAllOnesValue(SatWidth).zext(SrcElementWidth), DL, IntVT); in LowerVectorFP_TO_INT_SAT() 4069 Sat = DAG.getNode(ISD::UMIN, DL, IntVT, NativeCvt, MinC); in LowerVectorFP_TO_INT_SAT() 8520 EVT IntVT = VT.changeTypeToInteger(); in LowerFCOPYSIGN() local [all …]
|
| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 7630 EVT IntVT = Op.getValueType(); in LowerGET_DYNAMIC_AREA_OFFSET() local 7637 SDVTList VTs = DAG.getVTList(IntVT); in LowerGET_DYNAMIC_AREA_OFFSET()
|