| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMInstrNEON.td | 2524 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> 2527 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>; 2531 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> 2534 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>; 2539 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> 2542 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>; 2546 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> 2549 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>; 2554 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> 2557 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>; [all …]
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| H A D | ARMISelLowering.cpp | 17976 unsigned IntOp = cast<ConstantSDNode>(N.getOperand(1))->getZExtValue(); in SearchLoopIntrinsic() local 17977 if (IntOp != Intrinsic::test_start_loop_iterations && in SearchLoopIntrinsic() 17978 IntOp != Intrinsic::loop_decrement_reg) in SearchLoopIntrinsic() 18054 unsigned IntOp = cast<ConstantSDNode>(Int->getOperand(1))->getZExtValue(); in PerformHWLoopCombine() local 18067 if (IntOp == Intrinsic::test_start_loop_iterations) { in PerformHWLoopCombine()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/AsmParser/ |
| H A D | WebAssemblyAsmParser.cpp | 58 struct IntOp { struct 76 struct IntOp Int; 84 WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, IntOp I) in WebAssemblyOperand() 395 WebAssemblyOperand::IntOp{Val})); in parseSingleInteger() 466 WebAssemblyOperand::IntOp{-1})); in checkForP2AlignIfLoadStore() 481 WebAssemblyOperand::IntOp{static_cast<int64_t>(BT)})); in addBlockTypeOperand() 537 WebAssemblyOperand::IntOp{0}); in parseFunctionTableOperand()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXIntrinsics.td | 195 multiclass VOTE<NVPTXRegClass regclass, string mode, Intrinsic IntOp> { 198 [(set regclass:$dest, (IntOp Int1Regs:$pred))]>, 208 multiclass VOTE_SYNC<NVPTXRegClass regclass, string mode, Intrinsic IntOp> { 211 [(set regclass:$dest, (IntOp imm:$mask, Int1Regs:$pred))]>, 215 [(set regclass:$dest, (IntOp Int32Regs:$mask, Int1Regs:$pred))]>, 224 multiclass MATCH_ANY_SYNC<NVPTXRegClass regclass, string ptxtype, Intrinsic IntOp, 228 [(set Int32Regs:$dest, (IntOp imm:$mask, imm:$value))]>, 232 [(set Int32Regs:$dest, (IntOp Int32Regs:$mask, imm:$value))]>, 236 [(set Int32Regs:$dest, (IntOp imm:$mask, regclass:$value))]>, 240 [(set Int32Regs:$dest, (IntOp Int32Regs:$mask, regclass:$value))]>, [all …]
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| /openbsd-src/gnu/llvm/llvm/lib/Analysis/ |
| H A D | ScalarEvolution.cpp | 1178 const SCEV *IntOp = SCEVPtrToIntSinkingRewriter::rewrite(Op, *this); in getLosslessPtrToIntExpr() local 1179 assert(IntOp->getType()->isIntegerTy() && in getLosslessPtrToIntExpr() 1182 return IntOp; in getLosslessPtrToIntExpr() 1188 const SCEV *IntOp = getLosslessPtrToIntExpr(Op); in getPtrToIntExpr() local 1189 if (isa<SCEVCouldNotCompute>(IntOp)) in getPtrToIntExpr() 1190 return IntOp; in getPtrToIntExpr() 1192 return getTruncateOrZeroExtend(IntOp, Ty); in getPtrToIntExpr() 7982 const SCEV *IntOp = getPtrToIntExpr(Op, DstIntTy); in createSCEV() local 7983 if (isa<SCEVCouldNotCompute>(IntOp)) in createSCEV() 7985 return IntOp; in createSCEV()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrFormats.td | 6607 Intrinsic IntOp> { 6611 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>; 6619 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>; 6627 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>; 6636 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), 6641 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), 6646 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 52195 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1); in lowerX86FPLogicOp() local 52196 return DAG.getBitcast(VT, IntOp); in lowerX86FPLogicOp()
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