| /openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrFormats.td | 79 class I_16_ZX<string op, ImmLeaf ImmType, list<dag> pattern>
81 (outs GPR:$rz), (ins GPR:$rx,ImmType:$imm16),
93 class I_16_MOV<bits<5> sop, string op, ImmLeaf ImmType>
94 : CSKY32Inst<AddrModeNone, 0x3a, (outs GPR:$rz), (ins ImmType:$imm16),
96 [(set GPR:$rz, ImmType:$imm16)]> {
197 class I_12<bits<4> sop, string op, SDNode node, ImmLeaf ImmType>
199 (ins GPR:$rx, ImmType:$imm12), !strconcat(op, "\t$rz, $rx, $imm12"),
200 [(set GPR:$rz, (node GPR:$rx, ImmType:$imm12))]> {
264 class I_5_ZX<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
267 (ins CARRY:$cond, GPR:$false, GPR:$rx, ImmType:$imm5),
[all …]
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86InstrFormats.td | 81 // ImmType - This specifies the immediate type used by an instruction. This is
84 class ImmType<bits<4> val> {
87 def NoImm : ImmType<0>;
88 def Imm8 : ImmType<1>;
89 def Imm8PCRel : ImmType<2>;
90 def Imm8Reg : ImmType<3>; // Register encoded in [7:4].
91 def Imm16 : ImmType<4>;
92 def Imm16PCRel : ImmType<5>;
93 def Imm32 : ImmType<6>;
94 def Imm32PCRel : ImmType<7>;
[all …]
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| H A D | X86InstrArithmetic.td | 540 PatFrag loadnode, X86MemOperand memoperand, ImmType immkind,
568 ImmType ImmEncoding = immkind;
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| /openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoVPseudos.td | 2035 multiclass VPseudoBinaryV_VI<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> {
2036 defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
2386 multiclass VPseudoVGTR_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
2399 defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
2404 multiclass VPseudoVSALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
2417 defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
2423 multiclass VPseudoVSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
2436 defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
2441 multiclass VPseudoVSSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
2454 defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
[all …]
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| H A D | RISCVInstrInfoVSDPatterns.td | 123 Operand ImmType = simm5>
129 !cast<ComplexPattern>(SplatPat#_#ImmType),
130 ImmType>;
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| H A D | RISCVInstrInfo.td | 1179 class PatGprImm<SDPatternOperator OpNode, RVInst Inst, ImmLeaf ImmType>
1180 : Pat<(XLenVT (OpNode (XLenVT GPR:$rs1), ImmType:$imm)),
1181 (Inst GPR:$rs1, ImmType:$imm)>;
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| H A D | RISCVInstrInfoVVLPatterns.td | 516 Operand ImmType = simm5>
522 !cast<ComplexPattern>(SplatPat#_#ImmType),
523 ImmType>;
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| /openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | FastISel.h | 370 MVT ImmType);
|
| /openbsd-src/gnu/llvm/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXIntrinsics.td | 1922 NVPTXRegClass regclass, Operand ImmType,
1937 (ins Int32Regs:$src, ImmType:$b),
1940 (ins Int64Regs:$src, ImmType:$b),
1945 NVPTXRegClass regclass, Operand ImmType,
1959 (ins Int32Regs:$src, ImmType:$b, regclass:$c),
1962 (ins Int64Regs:$src, ImmType:$b, regclass:$c),
1965 (ins Int32Regs:$src, regclass:$b, ImmType:$c),
1968 (ins Int64Regs:$src, regclass:$b, ImmType:$c),
1972 (ins Int32Regs:$src, ImmType:$b, ImmType:$c),
1975 (ins Int64Regs:$src, ImmType:$b, ImmType:$c),
[all …]
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 1863 uint64_t Imm, MVT ImmType) { in fastEmit_ri_() argument
1884 Register MaterialReg = fastEmit_i(ImmType, ImmType, ISD::Constant, Imm); in fastEmit_ri_()
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| /openbsd-src/gnu/llvm/llvm/docs/TableGen/ |
| H A D | index.rst | 139 ImmType ImmT = NoImm;
|
| H A D | ProgRef.rst | 1972 ImmType ImmT = NoImm;
|