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Searched refs:INSERT_SUBVECTOR (Results 1 – 23 of 23) sorted by relevance

/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h558 INSERT_SUBVECTOR, enumerator
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp961 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
1414 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx); in SplitVecRes_INSERT_SUBVECTOR()
1422 Hi = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, Hi.getValueType(), Hi, SubVec, in SplitVecRes_INSERT_SUBVECTOR()
2801 case ISD::INSERT_SUBVECTOR: Res = SplitVecOp_INSERT_SUBVECTOR(N, OpNo); break; in SplitVectorOperand()
3106 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, Lo, Idx); in SplitVecOp_INSERT_SUBVECTOR()
3108 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, FirstInsertion, Hi, in SplitVecOp_INSERT_SUBVECTOR()
3894 case ISD::INSERT_SUBVECTOR: in WidenVectorResult()
4495 ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT), in WidenVecRes_OverflowOp()
4498 ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT), in WidenVecRes_OverflowOp()
5005 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WidenVT, InOp1, InOp2, Idx); in WidenVecRes_INSERT_SUBVECTOR()
[all …]
H A DLegalizeVectorOps.cpp1057 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandANY_EXTEND_VECTOR_INREG()
1116 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandZERO_EXTEND_VECTOR_INREG()
H A DSelectionDAGDumper.cpp298 case ISD::INSERT_SUBVECTOR: return "insert_subvector"; in getOperationName()
H A DDAGCombiner.cpp1805 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N); in visit()
21236 VecIn2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT1, in createBuildVecShuffle()
21264 VecIn2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT1, in createBuildVecShuffle()
22447 if (V.getOpcode() == ISD::INSERT_SUBVECTOR && in getSubVectorSrc()
22991 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
24011 TLI.isOperationLegalOrCustom(ISD::INSERT_SUBVECTOR, VT)) { in visitVECTOR_SHUFFLE()
24051 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, LHS, in visitVECTOR_SHUFFLE()
24601 SDValue NewINSERT = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), in visitINSERT_SUBVECTOR()
24610 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
24613 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0.getOperand(0), in visitINSERT_SUBVECTOR()
[all …]
H A DLegalizeIntegerTypes.cpp110 case ISD::INSERT_SUBVECTOR: in PromoteIntegerResult()
1680 case ISD::INSERT_SUBVECTOR: Res = PromoteIntOp_INSERT_SUBVECTOR(N); break; in PromoteIntegerOperand()
5398 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NOutVT, Vec, SubVec, Idx); in PromoteIntRes_INSERT_SUBVECTOR()
5650 SDValue Ext = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, PromVT, V0, V1, Idx); in PromoteIntOp_INSERT_SUBVECTOR()
5676 ResVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ResVec, Op, in PromoteIntOp_CONCAT_VECTORS()
H A DSelectionDAG.cpp3065 case ISD::INSERT_SUBVECTOR: { in computeKnownBits()
4465 case ISD::INSERT_SUBVECTOR: { in ComputeNumSignBits()
4736 case ISD::INSERT_SUBVECTOR: in canCreateUndefOrPoison()
6520 if (N1.getOpcode() == ISD::INSERT_SUBVECTOR && N2 == N1.getOperand(2) && in getNode()
6704 case ISD::INSERT_SUBVECTOR: { in getNode()
11666 return getNode(ISD::INSERT_SUBVECTOR, DL, WideVT, getUNDEF(WideVT), N, in WidenVector()
H A DTargetLowering.cpp847 case ISD::INSERT_SUBVECTOR: { in SimplifyMultipleUseDemandedBits()
1205 case ISD::INSERT_SUBVECTOR: { in SimplifyDemandedBits()
1376 if (Op0.getOpcode() == ISD::INSERT_SUBVECTOR && !VT.isScalableVector() && in SimplifyDemandedBits()
1391 TLO.DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT, NewAnd, in SimplifyDemandedBits()
3065 case ISD::INSERT_SUBVECTOR: { in SimplifyDemandedVectorElts()
3083 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in SimplifyDemandedVectorElts()
H A DSelectionDAGBuilder.cpp638 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, PartVT, DAG.getUNDEF(PartVT), in widenVectorToPartType()
7301 setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, ResultVT, Vec, SubVec, in visitIntrinsicCall()
H A DLegalizeDAG.cpp3049 case ISD::INSERT_SUBVECTOR: in ExpandNode()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86ISelLowering.h1229 (Op.getOpcode() == ISD::INSERT_SUBVECTOR && in isTargetCanonicalConstantNode()
1231 Op = Op.getOperand(Op.getOpcode() == ISD::INSERT_SUBVECTOR ? 1 : 0); in isTargetCanonicalConstantNode()
H A DX86ISelLowering.cpp922 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand); in X86TargetLowering()
1540 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal); in X86TargetLowering()
1642 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in X86TargetLowering()
1873 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal); in X86TargetLowering()
2008 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in X86TargetLowering()
2128 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32f16, Legal); in X86TargetLowering()
2169 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16f16, Legal); in X86TargetLowering()
2364 ISD::INSERT_SUBVECTOR, in X86TargetLowering()
6567 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx); in insertSubVector()
6592 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, Vec, in widenSubVector()
[all …]
H A DX86ISelDAGToDAG.cpp763 if (Root->getOpcode() == ISD::INSERT_SUBVECTOR && in IsProfitableToFold()
992 CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, CurDAG->getUNDEF(VT), in PreprocessISelDAG()
995 Res = CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, NarrowBCast, in PreprocessISelDAG()
1020 CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, CurDAG->getUNDEF(VT), in PreprocessISelDAG()
1023 Res = CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, NarrowBCast, in PreprocessISelDAG()
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp544 ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR}, in RISCVTargetLowering()
663 {ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR}, in RISCVTargetLowering()
755 {ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR}, in RISCVTargetLowering()
815 setOperationAction({ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR}, VT, in RISCVTargetLowering()
934 setOperationAction({ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR}, VT, in RISCVTargetLowering()
1870 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), V, Zero); in convertToScalableVector()
2834 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lowerScalarInsert()
2869 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lowerScalarInsert()
4045 case ISD::INSERT_SUBVECTOR: in LowerOperation()
4076 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, Vec, SubVec, in LowerOperation()
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H A DRISCVISelDAGToDAG.cpp1692 case ISD::INSERT_SUBVECTOR: { in Select()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp133 setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom); in initializeHVXLowering()
231 setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom); in initializeHVXLowering()
388 setOperationAction(ISD::INSERT_SUBVECTOR, BoolV, Custom); in initializeHVXLowering()
3205 case ISD::INSERT_SUBVECTOR: return LowerHvxInsertSubvector(Op, DAG); in LowerHvxOperation()
H A DHexagonISelLowering.cpp1644 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in HexagonTargetLowering()
1694 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
3337 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); in LowerOperation()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp953 ISD::INSERT_SUBVECTOR, ISD::STORE, ISD::BUILD_VECTOR}); in AArch64TargetLowering()
1221 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1283 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1308 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1364 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1429 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
5917 case ISD::INSERT_SUBVECTOR: in LowerOperation()
10277 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy), in WidenVector()
12723 SDValue NewLo = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, HalfVT, Lo, Vec1, in LowerINSERT_SUBVECTOR()
12728 DAG.getNode(ISD::INSERT_SUBVECTOR, DL, HalfVT, Hi, Vec1, in LowerINSERT_SUBVECTOR()
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H A DAArch64ISelDAGToDAG.cpp815 if (SV.getOpcode() != ISD::INSERT_SUBVECTOR) in checkHighLaneIndex()
4168 case ISD::INSERT_SUBVECTOR: { in Select()
/openbsd-src/gnu/llvm/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td724 def vector_insert_subvec : SDNode<"ISD::INSERT_SUBVECTOR",
730 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp279 case ISD::INSERT_SUBVECTOR: in SITargetLowering()
381 setOperationAction(ISD::INSERT_SUBVECTOR, in SITargetLowering()
385 setOperationAction(ISD::INSERT_SUBVECTOR, in SITargetLowering()
548 case ISD::INSERT_SUBVECTOR: in SITargetLowering()
4716 case ISD::INSERT_SUBVECTOR: in LowerOperation()
H A DAMDGPUISelLowering.cpp1594 Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad, in SplitVectorLoad()
1597 HiVT.isVector() ? ISD::INSERT_SUBVECTOR : ISD::INSERT_VECTOR_ELT, SL, in SplitVectorLoad()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1014 {ISD::BUILD_VECTOR, ISD::VECTOR_SHUFFLE, ISD::INSERT_SUBVECTOR, in ARMTargetLowering()
18691 case ISD::INSERT_SUBVECTOR: return PerformInsertSubvectorCombine(N, DCI); in PerformDAGCombine()