Home
last modified time | relevance | path

Searched refs:INS (Results 1 – 17 of 17) sorted by relevance

/openbsd-src/gnu/lib/libreadline/
H A DUSAGE4 Received: from arthur.INS.CWRU.Edu (root@arthur.INS.CWRU.Edu [129.22.8.215]) by odin.INS.CWRU.Edu w…
5 id UAA25349; Thu, 22 Jul 1999 20:37:54 -0400 (EDT) (from rms@gnu.org for <chet@odin.INS.CWRU.Edu>)
6 Received: from nike.ins.cwru.edu (root@nike.INS.CWRU.Edu [129.22.8.219]) by arthur.INS.CWRU.Edu wit…
/openbsd-src/regress/sys/arch/amd64/vmm/
H A Dvcpu.c50 const uint8_t INS[] = { 0x6C }; // ins es:[di],dx variable
57 .vrs_gprs[VCPU_REGS_RDX] = PCKBC_AUX, /* Port used by INS */
154 * INS dx, es:[di] ; read from port in dx in main()
160 memcpy(p, INS, sizeof(INS)); in main()
338 warnx("expected string instruction (INS)"); in main()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DSelectOptimize.cpp499 SmallPtrSet<const Instruction *, 2> INS; in convertProfitableSIGroups() local
500 INS.insert(ASI.begin(), ASI.end()); in convertProfitableSIGroups()
509 PN->addIncoming(getTrueOrFalseValue(SI, true, INS), TrueBlock); in convertProfitableSIGroups()
510 PN->addIncoming(getTrueOrFalseValue(SI, false, INS), FalseBlock); in convertProfitableSIGroups()
515 INS.erase(SI); in convertProfitableSIGroups()
H A DCodeGenPrepare.cpp7001 SmallPtrSet<const Instruction *, 2> INS; in optimizeSelectInst() local
7002 INS.insert(ASI.begin(), ASI.end()); in optimizeSelectInst()
7010 PN->addIncoming(getTrueOrFalseValue(SI, true, INS), TrueBlock); in optimizeSelectInst()
7011 PN->addIncoming(getTrueOrFalseValue(SI, false, INS), FalseBlock); in optimizeSelectInst()
7016 INS.erase(SI); in optimizeSelectInst()
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp657 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) in emitInterruptPrologueStub()
665 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) in emitInterruptPrologueStub()
674 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) in emitInterruptPrologueStub()
H A DMipsSEISelDAGToDAG.cpp247 SDNode *DSPCFWithCarry = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, Ops); in selectAddE()
258 CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps); in selectAddE()
1027 Opcode = Mips::INS; in trySelect()
H A DMipsInstrInfo.cpp856 case Mips::INS: in verifyInstruction()
H A DMipsSchedule.td137 def II_INS : InstrItinClass; // Any INS instruction
H A DMipsScheduleP5600.td206 def : InstRW<[P5600WriteAL2BitExt], (instrs EXT, INS)>;
H A DMipsScheduleGeneric.td48 CLO, CLZ, EXT, INS, LEA_ADDiu, LUi, NOP,
H A DMipsInstrInfo.td2448 def INS : MMRel, StdMMR6Rel, InsBase<"ins", GPR32Opnd, uimm5,
/openbsd-src/usr.sbin/mtrace/
H A Dmtrace.c838 #define INS 1 macro
867 have |= INS; in stat_line()
897 case INS: in stat_line()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64SchedCyclone.td349 // INS V[x],V[y] is a WriteV.
359 // INS V[x],R
H A DAArch64SchedTSV110.td673 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(DUP|INS)v.+lane")>;
681 def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^(INS|DUP)v.+gpr")>;
H A DAArch64InstrInfo.td5704 // AdvSIMD INS/DUP instructions
5869 defm INS : SIMDIns;
5997 // index type and INS extension
6024 ValueType VTScal, Instruction INS> {
6028 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
6033 (INS V128:$src, imm:$Immd,
6039 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
6047 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
6099 // INS.
H A DAArch64InstrFormats.td7479 // AdvSIMD INS/DUP instructions
7768 // For all forms of the INS instruction, the "mov" mnemonic is the
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstrInfo.td2270 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)