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Searched refs:IMM (Results 1 – 25 of 37) sorted by relevance

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/openbsd-src/gnu/gcc/gcc/config/m68k/
H A Dlb1sf68.asm70 #define IMM(x) CONCAT1 (__IMMEDIATE_PREFIX__, x) macro
288 movew IMM (0),a0@(STICK)
333 cmpw IMM (SINGLE_FLOAT),d6
335 cmpl IMM (SINGLE_FLOAT),d6
356 trap IMM (FPTRAP) | and trap
401 cmpl IMM (0x10000), d1 /* divisor >= 2 ^ 16 ? */
415 L4: lsrl IMM (1), d1 /* shift divisor */
416 lsrl IMM (1), d0 /* shift dividend */
417 cmpl IMM (0x10000), d1 /* still divisor >= 2 ^ 16 ? */
420 andl IMM (0xffff), d0 /* mask out divisor, ignore remainder */
[all …]
/openbsd-src/gnu/usr.bin/gcc/gcc/config/m68k/
H A Dlb1sf68.asm70 #define IMM(x) CONCAT1 (__IMMEDIATE_PREFIX__, x) macro
218 movew IMM (0),a0@(STICK)
263 cmpw IMM (SINGLE_FLOAT),d6
265 cmpl IMM (SINGLE_FLOAT),d6
286 trap IMM (FPTRAP) | and trap
331 cmpl IMM (0x10000), d1 /* divisor >= 2 ^ 16 ? */
345 L4: lsrl IMM (1), d1 /* shift divisor */
346 lsrl IMM (1), d0 /* shift dividend */
347 cmpl IMM (0x10000), d1 /* still divisor >= 2 ^ 16 ? */
350 andl IMM (0xffff), d0 /* mask out divisor, ignore remainder */
[all …]
/openbsd-src/gnu/usr.bin/binutils-2.17/include/opcode/
H A Dmaxq.h64 IMM = 0x10, /* Immediate value. */ enumerator
128 {REG | MEM | IMM | DISP, 0}, MAX, 0x11},
133 {REG | MEM | IMM | DISP, 0}, MAX, 0x12},
138 {REG | MEM | IMM | DISP, 0}, MAX, 0x13},
173 {IMM | REG | MEM | DISP, 0}, MAX, 0x14},
176 {IMM | REG | MEM | DISP, 0}, MAX, 0x16},
179 {IMM | REG | MEM | DISP, 0}, MAX, 0x15},
182 {IMM | REG | MEM | DISP, 0}, MAX, 0x17},
187 {IMM | REG | MEM | DISP, 0}, MAX, 0xA4},
190 {IMM | REG | MEM | DISP, 0}, MAX, 0xA5},
[all …]
H A Dh8300.h52 IMM = 0x0400, enumerator
123 IMM3 = IMM | L_3,
124 IMM4 = IMM | L_4,
125 IMM5 = IMM | L_5,
126 IMM3NZ = IMM | L_3NZ,
127 IMM2 = IMM | L_2,
129 IMM8 = IMM | SRC | L_8,
130 IMM8U = IMM | SRC | L_8U,
131 IMM16 = IMM | SRC | L_16,
132 IMM16U = IMM | SRC | L_16U,
[all …]
/openbsd-src/gnu/llvm/compiler-rt/lib/builtins/arm/
H A Dudivsi3.S183 #define IMM # macro
199 lsls r2, r1, IMM shift; \
214 cmp r0, r1, lsl IMM shift; \
216 WIDE(addhs) r3, r3, IMM (1 << shift); \
217 WIDE(subhs) r0, r0, r1, lsl IMM shift
H A Dudivmodsi4.S110 #define IMM # macro
113 cmp r0, r1, lsl IMM shift; \
115 WIDE(addhs) r3, r3, IMM (1 << shift); \
116 WIDE(subhs) r0, r0, r1, lsl IMM shift
H A Dumodsi3.S102 #define IMM # macro
105 cmp r0, r1, lsl IMM shift; \
107 WIDE(subhs) r0, r0, r1, lsl IMM shift
/openbsd-src/sys/arch/powerpc64/powerpc64/
H A Ddb_disasm.c446 { "mtfsfi", 0xfc0007fe, 0xfc00010c, "%{RC} %{crfD},f%{C},%{IMM}" },
825 int IMM; in disasm_process_field() local
826 IMM = extract_field(instr, 31, 16); in disasm_process_field()
827 if (IMM & 0x8000) in disasm_process_field()
828 IMM |= ~0x7fff; in disasm_process_field()
829 snprintf(lbuf, sizeof (lbuf), "%d", IMM); in disasm_process_field()
835 u_int IMM; in disasm_process_field() local
836 IMM = extract_field(instr, 31, 16); in disasm_process_field()
837 snprintf(lbuf, sizeof (lbuf), "0x%x", IMM); in disasm_process_field()
/openbsd-src/sys/arch/powerpc/ddb/
H A Ddb_disasm.c446 { "mtfsfi", 0xfc0007fe, 0xfc00010c, "%{RC} %{crfD},f%{C},%{IMM}" },
825 int IMM; in disasm_process_field() local
826 IMM = extract_field(instr, 31, 16); in disasm_process_field()
827 if (IMM & 0x8000) in disasm_process_field()
828 IMM |= ~0x7fff; in disasm_process_field()
829 snprintf(lbuf, sizeof (lbuf), "%d", IMM); in disasm_process_field()
835 u_int IMM; in disasm_process_field() local
836 IMM = extract_field(instr, 31, 16); in disasm_process_field()
837 snprintf(lbuf, sizeof (lbuf), "0x%x", IMM); in disasm_process_field()
/openbsd-src/gnu/llvm/llvm/lib/Target/M68k/
H A DM68kInstrShiftRotate.td41 /// 1 1 1 0 | REG/IMM | D | SIZE |R/I| OP | REG
46 // REG/IMM
/openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats.td77 // Format< OP[6] | RZ[5] | RX[5] | IMM[16] >
91 // Format< OP[6] | SOP[5] | RZ[5] | IMM[16] >
141 // Format< OP[6] | SOP[5] | RX[5] | 00000000000000[14] | IMM[2] >
195 // Format< OP[6] | RZ[5] | RX[5] | SOP[4] | IMM[12] >
262 // Format< OP[6] | RZ[5] | RX[5] | SOP[6] | PCODE[5] | IMM[5]>
280 // Format< OP[6] | IMM[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5]>
386 // Format< OP[6] | RY[5] | RX[5] | SOP[6] | PCODE[5] | IMM[5]>
469 // Format< OP[6] | IMM[5] | RX[5] | SOP[6] | PCODE[5] | 00000 >
486 // Format< OP[6] | IMM[5] | 00000[5] | SOP[6] | PCODE[5] | RZ[5]>
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCInstrP10.td29 // * IMM - immediate (where signedness matters,
48 // The operand is an 8-bit immediate (IMM), the destination (XT)
303 // X-Form: [PO T IMM VRB XO TX]
309 bits<5> IMM;
313 let Inst{11-15} = IMM;
327 bits<8> IMM;
337 let Inst{24-31} = IMM;
523 bits<3> IMM;
532 let Inst{29-31} = IMM;
1650 vsrc:$XC, u8imm:$IMM),
[all …]
H A DPPCInstrFormats.td2000 bits<5> IMM;
2005 let Inst{11-15} = IMM;
/openbsd-src/gnu/usr.bin/binutils-2.17/gas/config/
H A Dtc-h8300.c819 op->mode = IMM; in get_operand()
1136 else if (x_mode == IMM && op_mode != IMM) in get_specific()
1166 else if ((op_mode == DISP || op_mode == IMM || op_mode == ABS in get_specific()
1285 char *t = ((operand->mode & MODE) == IMM) ? "#" : "@"; in do_a_fix_imm()
1456 else if (c2 == IMM || c2 == PCREL || c2 == ABS in build_bytes()
1579 if (x_mode == IMM || x_mode == DISP) in build_bytes()
H A Dtc-maxq.c1726 i.types[this_operand] = IMM; in maxq20_operand()
1966 case IMM: in match_operands()
2187 if (i.operands == 2 && i.types[0] == IMM) in match_filters()
2563 else if (i.imm_operands == 1 && ((i.op.src[0] & IMM) == IMM)) in decode_insn()
/openbsd-src/gnu/usr.bin/binutils/gas/config/
H A Dtc-h8300.c838 op->mode = IMM; in get_operand()
1154 else if (x_mode == IMM && op_mode != IMM) in get_specific()
1184 else if ((op_mode == DISP || op_mode == IMM || op_mode == ABS in get_specific()
1312 char *t = ((operand->mode & MODE) == IMM) ? "#" : "@"; in do_a_fix_imm()
1483 else if (c2 == IMM || c2 == PCREL || c2 == ABS in build_bytes()
1606 if (x_mode == IMM || x_mode == DISP) in build_bytes()
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZPatterns.td40 // respectively. MODE is the addressing mode and IMM is the type
49 // memory location. IMM is the type of the second operand.
/openbsd-src/gnu/usr.bin/binutils/opcodes/
H A Diq2000-opc.c434 { { MNEM, ' ', OP (RT_RS), ',', OP (IMM), 0 } },
440 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (IMM), 0 } },
446 { { MNEM, ' ', OP (RT_RS), ',', OP (IMM), 0 } },
452 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (IMM), 0 } },
2797 { { MNEM, ' ', OP (RS), ',', OP (IMM), 0 } },
2869 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (IMM), 0 } },
2875 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (IMM), 0 } },
H A Dh8300-dis.c211 else if ((x & MODE) == IMM)
/openbsd-src/gnu/usr.bin/binutils-2.17/opcodes/
H A Diq2000-opc.c434 { { MNEM, ' ', OP (RT_RS), ',', OP (IMM), 0 } },
440 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (IMM), 0 } },
446 { { MNEM, ' ', OP (RT_RS), ',', OP (IMM), 0 } },
452 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (IMM), 0 } },
2797 { { MNEM, ' ', OP (RS), ',', OP (IMM), 0 } },
2869 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (IMM), 0 } },
2875 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (IMM), 0 } },
H A Dh8300-dis.c200 else if ((x & MODE) == IMM) in print_one_arg()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSMInstructions.td841 // 1. IMM offset
847 // 2. 32-bit IMM offset on CI
860 // 4. SGPR+IMM offset
882 // 2. 32-bit IMM offset on CI
/openbsd-src/gnu/usr.bin/binutils/include/opcode/
H A Dh8300.h51 IMM = 0x0400, enumerator
122 IMM3 = IMM | L_3,
123 IMM4 = IMM | L_4,
124 IMM5 = IMM | L_5,
125 IMM3NZ = IMM | L_3NZ,
126 IMM2 = IMM | L_2,
128 IMM8 = IMM | SRC | L_8,
129 IMM8U = IMM | SRC | L_8U,
130 IMM16 = IMM | SRC | L_16,
131 IMM16U = IMM | SRC | L_16U,
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMScheduleSwift.td366 (instregex "LD(RB|R)(_|T_)(POST|PRE)_(IMM|REG)", "LDRH(_PRE|_POST)",
367 "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)",
H A DARMScheduleR52.td298 (instregex "LD(RB|R)(_|T_)(POST|PRE)_(IMM|REG)", "LDRH(_PRE|_POST)",
299 "LDRBT_POST$", "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)",

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