Home
last modified time | relevance | path

Searched refs:HiReg (Results 1 – 17 of 17) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonCopyToCombine.cpp805 Register HiReg = HiOperand.getReg(); in emitCombineRI() local
813 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
821 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
845 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
856 Register HiReg = HiOperand.getReg(); in emitCombineRR() local
873 .addReg(HiReg, HiRegKillFlag) in emitCombineRR()
H A DHexagonPatterns.td121 def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG $Rs, isub_hi)>;
544 (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>;
547 (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>;
563 (A2_combine_ll (HiReg $Rs), (LoReg $Rs))>;
574 (C2_mux (C2_cmpeqi (HiReg $Rs), (i32 0)), (LoReg $Rs), (i32 -1))>;
901 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
905 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
915 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
1124 (A2_swiz (HiReg $Rss)))>;
1127 def: Pat<(bswap V2I32:$Rs), (Combinew (A2_swiz (HiReg $Rs)),
[all …]
H A DHexagonIntrinsics.td95 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
97 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
H A DHexagonFrameLowering.cpp1126 Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi); in insertCFIInstructionsAt() local
1128 unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true); in insertCFIInstructionsAt()
/openbsd-src/gnu/llvm/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.h52 void splitReg(Register Reg, Register &LoReg, Register &HiReg) const;
H A DAVRRegisterInfo.cpp306 Register &HiReg) const { in splitReg()
310 HiReg = getSubReg(Reg, AVR::sub_hi); in splitReg()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp2186 Register HiReg = MRI->createVirtualRegister(DstRC); in selectG_TRUNC() local
2189 BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), HiReg) in selectG_TRUNC()
2198 .addReg(HiReg) // $src0 in selectG_TRUNC()
2212 .addReg(HiReg); in selectG_TRUNC()
2215 .addReg(HiReg) in selectG_TRUNC()
2370 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_SZA_EXT() local
2373 BuildMI(MBB, I, DL, TII.get(AMDGPU::S_ASHR_I32), HiReg) in selectG_SZA_EXT()
2377 BuildMI(MBB, I, DL, TII.get(AMDGPU::S_MOV_B32), HiReg) in selectG_SZA_EXT()
2383 .addReg(HiReg) in selectG_SZA_EXT()
2483 Register HiReg = MRI->createVirtualRegister(RC); in selectG_CONSTANT() local
[all …]
H A DSILoadStoreOptimizer.cpp186 Register HiReg; member
1930 assert((TRI->getRegSizeInBits(Addr.Base.HiReg, *MRI) == 32 || in computeBase()
1957 .addReg(Addr.Base.HiReg, 0, Addr.Base.HiSubReg) in computeBase()
2060 Addr.Base.HiReg = BaseHi.getReg(); in processBaseWithConstOffset()
2107 LLVM_DEBUG(dbgs() << " BASE: {" << MAddr.Base.HiReg << ", " in promoteConstantOffsetToImm()
2165 MAddrNext.Base.HiReg != MAddr.Base.HiReg || in promoteConstantOffsetToImm()
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp309 Register HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
325 std::swap(LoReg, HiReg); in expandBuildPairF64()
328 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, in expandBuildPairF64()
H A DMipsSEInstrInfo.cpp828 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
876 .addReg(HiReg); in expandBuildPairF64()
881 .addReg(HiReg); in expandBuildPairF64()
H A DMipsISelLowering.cpp2954 MCRegister HiReg = State.AllocateReg(IntRegs); in CC_MipsO32() local
2955 assert(HiReg); in CC_MipsO32()
2957 CCValAssign::getCustomReg(ValNo, ValVT, HiReg, LocVT, LocInfo)); in CC_MipsO32()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp5241 unsigned LoReg, HiReg; in Select() local
5255 HiReg = X86::EDX; in Select()
5265 HiReg = X86::RDX; in Select()
5341 assert(HiReg && "Register for high half is not defined!"); in Select()
5342 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, in Select()
5380 unsigned LoReg, HiReg, ClrReg; in Select() local
5385 LoReg = X86::AL; ClrReg = HiReg = X86::AH; in Select()
5389 LoReg = X86::AX; HiReg = X86::DX; in Select()
5394 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX; in Select()
5398 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX; in Select()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp1975 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) { in CMSEPushCalleeSaves() local
1979 .addReg(HiReg, LiveRegs.contains(HiReg) ? 0 : RegState::Undef) in CMSEPushCalleeSaves()
1981 --HiReg; in CMSEPushCalleeSaves()
/openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1283 Register HiReg = VA.getLocReg(); in LowerCall_64() local
1286 HiReg = toCallerWindow(HiReg); in LowerCall_64()
1290 RegsToPass.push_back(std::make_pair(HiReg, Hi64)); in LowerCall_64()
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp11068 Register HiReg = MI.getOperand(1).getReg(); in emitReadCycleWidePseudo() local
11072 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), HiReg) in emitReadCycleWidePseudo()
11083 .addReg(HiReg) in emitReadCycleWidePseudo()
11104 Register HiReg = MI.getOperand(1).getReg(); in emitSplitF64Pseudo() local
11120 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg) in emitSplitF64Pseudo()
11139 Register HiReg = MI.getOperand(2).getReg(); in emitBuildPairF64Pseudo() local
11154 .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill())) in emitBuildPairF64Pseudo()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp7496 unsigned Reg, unsigned HiReg, in checkLowRegisterList() argument
7504 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp12521 Register HiReg = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
12523 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269); in EmitInstrWithCustomInserter()
12530 .addReg(HiReg) in EmitInstrWithCustomInserter()