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Searched refs:GPRC (Results 1 – 10 of 10) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoC.td303 def C_ADDI4SPN : RVInst16CIW<0b000, 0b00, (outs GPRC:$rd),
322 def C_LW : CLoad_ri<0b010, "c.lw", GPRC, uimm7_lsb00>,
341 def C_LD : CLoad_ri<0b011, "c.ld", GPRC, uimm8_lsb000>,
356 def C_SW : CStore_rri<0b110, "c.sw", GPRC, uimm7_lsb00>,
375 def C_SD : CStore_rri<0b111, "c.sd", GPRC, uimm8_lsb000>,
453 def C_SRLI : Shift_right<0b00, "c.srli", GPRC, uimmlog2xlennonzero>,
455 def C_SRAI : Shift_right<0b01, "c.srai", GPRC, uimmlog2xlennonzero>,
459 def C_ANDI : RVInst16CB<0b100, 0b01, (outs GPRC:$rs1_wb), (ins GPRC:$rs1, simm6:$imm),
468 def C_SUB : CS_ALU<0b100011, 0b00, "c.sub", GPRC>,
470 def C_XOR : CS_ALU<0b100011, 0b01, "c.xor", GPRC>,
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H A DRISCVRegisterInfo.td74 // are not part of GPRC, the most restrictive register class used by the
158 def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add
H A DRISCVInstrInfo.td144 def GPRCMem : MemOperand<GPRC>;
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp758 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerDynamicAlloc() local
759 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerDynamicAlloc()
824 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in prepareDynamicAlloca() local
865 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca()
873 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca()
967 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRSpilling() local
969 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
981 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
1012 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRRestore() local
1014 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
[all …]
H A DPPCRegisterInfo.td283 def GPRC : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "R%u", 2, 12),
291 let AltOrders = [(add (sub GPRC, R2), R2),
315 def GPRC_NOR0 : RegisterClass<"PPC", [i32,f32], 32, (add (sub GPRC, R0), ZERO)> {
468 def gprc : RegisterOperand<GPRC> {
540 def spe4rc : RegisterOperand<GPRC> {
H A DPPCISelLowering.cpp11767 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in EmitPartwordAtomicBinary() local
11770 Register Shift1Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11772 isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11773 Register Incr2Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11774 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11775 Register Mask2Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11776 Register Mask3Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11777 Register Tmp2Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11778 Register Tmp3Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11779 Register Tmp4Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
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H A DPPCFrameLowering.cpp2292 const TargetRegisterClass &GPRC = PPC::GPRCRegClass; in addScavengingSpillSlot() local
2294 const TargetRegisterClass &RC = Subtarget.isPPC64() ? G8RC : GPRC; in addScavengingSpillSlot()
H A DPPCInstrVSX.td2675 (COPY_TO_REGCLASS (XVTDIVDP $A, $B), GPRC)>;
2677 (COPY_TO_REGCLASS (XVTDIVSP $A, $B), GPRC)>;
2679 (COPY_TO_REGCLASS (XVTSQRTDP $A), GPRC)>;
2681 (COPY_TO_REGCLASS (XVTSQRTSP $A), GPRC)>;
/openbsd-src/gnu/llvm/llvm/docs/
H A DCodeGenerator.rst1124 def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst),
1128 def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff),
1129 (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>;
/openbsd-src/sys/dev/pci/
H A Dif_em_hw.c8285 temp = E1000_READ_REG(hw, GPRC); in em_clear_hw_cntrs()