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Searched refs:GPR (Results 1 – 25 of 245) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoXVentana.td20 : RVInstR<0b0000000, funct3, OPC_CUSTOM_3, (outs GPR:$rd),
21 (ins GPR:$rs1, GPR:$rs2), opcodestr,
33 def : Pat<(select GPR:$rc, GPR:$rs1, (i64 0)),
35 def : Pat<(select GPR:$rc, (i64 0), GPR:$rs1),
38 def : Pat<(select (i64 (setne GPR:$rc, (i64 0))), GPR:$rs1, (i64 0)),
39 (VT_MASKC GPR:$rs1, GPR:$rc)>;
40 def : Pat<(select (i64 (seteq GPR:$rc, (i64 0))), GPR:$rs1, (i64 0)),
41 (VT_MASKCN GPR:$rs1, GPR:$rc)>;
42 def : Pat<(select (i64 (setne GPR:$rc, (i64 0))), (i64 0), GPR:$rs1),
43 (VT_MASKCN GPR:$rs1, GPR:$rc)>;
[all …]
H A DRISCVInstrInfoA.td21 (outs GPR:$rd), (ins GPRMemZeroOffset:$rs1),
36 (outs GPR:$rd), (ins GPRMemZeroOffset:$rs1, GPR:$rs2),
48 def : Pat<(StoreOp (AddrRegImm GPR:$rs1, simm12:$imm12), (vt StTy:$rs2)),
49 (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
116 defm : AtomicStPat<atomic_store_8, SB, GPR>;
117 defm : AtomicStPat<atomic_store_16, SH, GPR>;
118 defm : AtomicStPat<atomic_store_32, SW, GPR>;
123 defm : AtomicStPat<atomic_store_64, SD, GPR, i64>;
153 def : Pat<(atomic_load_sub_32_monotonic GPR:$addr, GPR:$incr),
154 (AMOADD_W GPR:$addr, (SUB X0, GPR:$incr))>;
[all …]
H A DRISCVInstrInfoZb.td241 def non_imm12 : PatLeaf<(XLenVT GPR:$a), [{
274 : RVInstR<funct7, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
282 : RVInstIShift<imm11_7, funct3, opcode, (outs GPR:$rd),
283 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
289 : RVInstIShiftW<imm11_5, funct3, opcode, (outs GPR:$rd),
290 (ins GPR:$rs1, uimm5:$shamt), opcodestr,
297 : RVInstIShiftW<imm11_5, funct3, opcode, (outs GPR:$rd),
298 (ins GPR:$rs1, shfl_uimm:$shamt), opcodestr,
304 : RVInstR4<funct2, funct3, opcode, (outs GPR:$rd),
305 (ins GPR:$rs1, GPR:$rs2, GPR:$rs3), opcodestr, argstr>;
[all …]
H A DRISCVInstrInfo.td135 def GPRMemZeroOffset : MemOperand<GPR> {
140 def GPRMem : MemOperand<GPR>;
500 (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
509 : RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPRMem:$rs1, simm12:$imm12),
513 : RVInstR<funct7, 0b100, OPC_SYSTEM, (outs GPR:$rd),
525 (ins GPR:$rs2, GPRMem:$rs1, simm12:$imm12),
530 (ins GPR:$rs2, GPRMemZeroOffset:$rs1),
538 : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
544 : RVInstIShift<imm11_7, funct3, OPC_OP_IMM, (outs GPR:$rd),
545 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
[all …]
H A DRISCVInstrInfoM.td95 def : Pat<(and (riscv_divuw (assertzexti32 GPR:$rs1),
96 (assertzexti32 GPR:$rs2)), 0xffffffff),
97 (DIVU GPR:$rs1, GPR:$rs2)>;
98 def : Pat<(and (riscv_remuw (assertzexti32 GPR:$rs1),
99 (assertzexti32 GPR:$rs2)), 0xffffffff),
100 (REMU GPR:$rs1, GPR:$rs2)>;
105 def : Pat<(srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2))),
106 (REMW GPR:$rs1, GPR:$rs2)>;
114 def : Pat<(i64 (mul (and GPR:$rs1, 0xffffffff), (and GPR:$rs2, 0xffffffff))),
115 (MULHU (SLLI GPR:$rs1, 32), (SLLI GPR:$rs2, 32))>;
H A DRISCVInstrInfoVVLPatterns.td439 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>;
460 GPR:$vl, sew, TAIL_AGNOSTIC)>;
473 GPR:$vl, sew, TAIL_UNDISTURBED_MASK_UNDISTURBED)>;
499 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>;
511 SplatPat, GPR>;
538 SplatPat, GPR>;
557 SplatPat, GPR>;
572 SplatPat, GPR>;
600 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>;
626 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
[all …]
H A DRISCVInstrInfoD.td70 def DX : ExtInfo_rr<DExt, FPR64, GPR>;
71 def DX_INX : ExtInfo_rr<ZdinxExt, FPR64INX, GPR>;
72 def DX_IN32X : ExtInfo_rr<Zdinx32Ext, FPR64IN32X, GPR>;
73 def DX_64 : ExtInfo_rr<D64Ext, FPR64, GPR>;
77 def XD : ExtInfo_rr<DExt, GPR, FPR64>;
78 def XD_INX : ExtInfo_rr<ZdinxExt, GPR, FPR64INX>;
79 def XD_IN32X : ExtInfo_rr<Zdinx32Ext, GPR, FPR64IN32X>;
80 def XD_64 : ExtInfo_rr<D64Ext, GPR, FPR64>;
188 def FMV_X_D : FPUnaryOp_r<0b1110001, 0b00000, 0b000, GPR, FPR64, "fmv.x.d">,
200 def FMV_D_X : FPUnaryOp_r<0b1111001, 0b00000, 0b000, FPR64, GPR, "fmv.d.x">,
[all …]
H A DRISCVInstrInfoF.td122 def FX : ExtInfo_rr<FExt, FPR32, GPR>;
123 def FX_INX : ExtInfo_rr<ZfinxExt, FPR32INX, GPR>;
124 def FX_64 : ExtInfo_rr<F64Ext, FPR32, GPR>;
125 def FX_INX_64 : ExtInfo_rr<Zfinx64Ext, FPR32INX, GPR>;
126 def XF : ExtInfo_rr<FExt, GPR, FPR32>;
127 def XF_64 : ExtInfo_rr<F64Ext, GPR, FPR32>;
128 def XF_INX : ExtInfo_rr<ZfinxExt, GPR, FPR32INX>;
129 def XF_INX_64 : ExtInfo_rr<Zfinx64Ext, GPR, FPR32INX>;
289 : RVInstR<funct7, funct3, OPC_OP_FP, (outs GPR:$rd),
378 def FMV_X_W : FPUnaryOp_r<0b1110000, 0b00000, 0b000, GPR, FPR32, "fmv.x.w">,
[all …]
H A DRISCVInstrInfoZk.td44 : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
51 : RVInstR<{0b00, funct5}, 0b000, OPC_OP, (outs GPR:$rd),
52 (ins GPR:$rs1, GPR:$rs2, byteselect:$bs),
60 : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, rnum:$rnum),
137 : Pat<(OpNode GPR:$rs1, GPR:$rs2, i8:$imm),
138 (Inst GPR:$rs1, GPR:$rs2, byteselect:$imm)>;
154 def : Pat<(int_riscv_aes64ks1i GPR:$rs1, i32:$rnum),
155 (AES64KS1I GPR:$rs1, rnum:$rnum)>;
H A DRISCVInstrInfoZfh.td56 def XH : ExtInfo_rr<ZfhExt, GPR, FPR16>;
57 def XH_INX : ExtInfo_rr<ZhinxExt, GPR, FPR16INX>;
58 def HX : ExtInfo_rr<ZfhExt, FPR16, GPR>;
59 def HX_INX : ExtInfo_rr<ZhinxExt, FPR16INX, GPR>;
60 def XH_64 : ExtInfo_rr<Zfh64Ext, GPR, FPR16>;
61 def HX_64 : ExtInfo_rr<Zfh64Ext, FPR16, GPR>;
62 def XH_INX_64 : ExtInfo_rr<Zhinx64Ext, GPR, FPR16INX>;
63 def HX_INX_64 : ExtInfo_rr<Zhinx64Ext, FPR16INX, GPR>;
169 def FMV_X_H : FPUnaryOp_r<0b1110010, 0b00000, 0b000, GPR, FPR16, "fmv.x.h">,
173 def FMV_H_X : FPUnaryOp_r<0b1111010, 0b00000, 0b000, FPR16, GPR, "fmv.h.x">,
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.td172 def GPRMemAtomic : RegisterOperand<GPR> {
386 : Fmt3R<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk), opstr, "$rd, $rj, $rk">;
388 : Fmt2R<op, (outs GPR:$rd), (ins GPR:$rj), opstr, "$rd, $rj">;
391 : Fmt3RI2<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk, ImmOpnd:$imm2), opstr,
394 : Fmt3RI3<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk, ImmOpnd:$imm3), opstr,
397 : Fmt2RI5<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm5), opstr,
400 : Fmt2RI6<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm6), opstr,
403 : Fmt2RI12<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm12), opstr,
406 : Fmt2RI16<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm16), opstr,
409 : Fmt1RI20<op, (outs GPR:$rd), (ins ImmOpnd:$imm20), opstr, "$rd, $imm20">;
[all …]
H A DLoongArchFloat32InstrInfo.td99 def MOVGR2FR_W : FP_MOV<0b0000000100010100101001, "movgr2fr.w", FPR32, GPR>;
100 def MOVFR2GR_S : FP_MOV<0b0000000100010100101101, "movfr2gr.s", GPR, FPR32>;
101 def MOVGR2FCSR : FP_MOV<0b0000000100010100110000, "movgr2fcsr", FCSR, GPR>;
102 def MOVFCSR2GR : FP_MOV<0b0000000100010100110010, "movfcsr2gr", GPR, FCSR>;
105 def MOVGR2CF : FP_MOV<0b0000000100010100110110, "movgr2cf", CFR, GPR>;
106 def MOVCF2GR : FP_MOV<0b0000000100010100110111, "movcf2gr", GPR, CFR>;
127 (ins CFR:$ccd, GPR:$rj, grlenimm:$imm)>;
130 (ins GPR:$rj, grlenimm:$imm)>;
288 // GPR -> FPR
289 def : Pat<(loongarch_movgr2fr_w_la64 GPR:$src), (MOVGR2FR_W GPR:$src)>;
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.td388 let MIOperandInfo = (ops GPR, uimm5);
473 [(set GPR:$rz, (or GPR:$rx, uimm16:$imm16))]>;
478 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
479 [(set GPR:$rz, (shl GPR:$rx, uimm5:$imm5))]>;
481 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
482 [(set GPR:$rz, (srl GPR:$rx, uimm5:$imm5))]>;
484 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
485 [(set GPR:$rz, (sra GPR:$rx, uimm5:$imm5))]>;
487 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
488 [(set GPR:$rz, (rotl GPR:$rx, uimm5:$imm5))]>;
[all …]
H A DCSKYInstrInfoF2.td61 def f2FLD_S : F2_LDST_S<0b0, "fld", (outs FPR32Op:$vrz), (ins GPR:$rx, uimm8_2:$imm8)>;
63 def f2FLD_D : F2_LDST_D<0b0, "fld", (outs FPR64Op:$vrz), (ins GPR:$rx, uimm8_2:$imm8)>;
66 def f2FST_S : F2_LDST_S<0b1, "fst", (outs), (ins FPR32Op:$vrz, GPR:$rx, uimm8_2:$imm8)>;
68 def f2FST_D : F2_LDST_D<0b1, "fst", (outs), (ins FPR64Op:$vrz, GPR:$rx, uimm8_2:$imm8)>;
72 def f2FSTM_S : F2_LDSTM_S<0b1, 0, "fstm", (outs), (ins GPR:$rx, regseq_f2:$regs, variable_ops)>;
74 def f2FSTM_D : F2_LDSTM_D<0b1, 0, "fstm", (outs), (ins GPR:$rx, regseq_d2:$regs, variable_ops)>;
76 …def f2FSTMU_S : F2_LDSTM_S<0b1, 0b100, "fstmu", (outs), (ins GPR:$rx, regseq_f2:$regs, variable_op…
78 …def f2FSTMU_D : F2_LDSTM_D<0b1, 0b100, "fstmu", (outs), (ins GPR:$rx, regseq_d2:$regs, variable_op…
82 def f2FLDM_S : F2_LDSTM_S<0b0, 0, "fldm", (outs), (ins GPR:$rx, regseq_f2:$regs, variable_ops)>;
84 def f2FLDM_D : F2_LDSTM_D<0b0, 0, "fldm", (outs), (ins GPR:$rx, regseq_d2:$regs, variable_ops)>;
[all …]
H A DCSKYInstrFormats.td81 (outs GPR:$rz), (ins GPR:$rx,ImmType:$imm16),
94 : CSKY32Inst<AddrModeNone, 0x3a, (outs GPR:$rz), (ins ImmType:$imm16),
96 [(set GPR:$rz, ImmType:$imm16)]> {
110 : CSKY32Inst<AddrModeNone, 0x3a, (outs GPR:$rz), ins,
132 : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx),
145 (ins GPR:$rx, operand:$imm2),
172 (ins GPR:$rx, operand:$imm16), !strconcat(op, "\t$rx, $imm16"), []> {
184 : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx, operand:$imm16),
198 : CSKY32Inst<AddrModeNone, 0x39, (outs GPR:$rz),
199 (ins GPR:$rx, ImmType:$imm12), !strconcat(op, "\t$rz, $rx, $imm12"),
[all …]
H A DCSKYInstrInfoF1.td146 def FMFVRL : F_XZ_GF<3, 0b011001, (outs GPR:$rz), (ins sFPR32Op:$vrx),
147 "fmfvrl\t$rz, $vrx", [(set GPR:$rz, (bitconvert sFPR32Op:$vrx))]>;
148 def FMTVRL : F_XZ_FG<3, 0b011011, (outs sFPR32Op:$vrz), (ins GPR:$rx),
149 "fmtvrl\t$vrz, $rx", [(set sFPR32Op:$vrz, (bitconvert GPR:$rx))]>;
153 def FMFVRL_D : F_XZ_GF<3, 0b011001, (outs GPR:$rz), (ins sFPR64Op:$vrx),
155 def FMFVRH_D : F_XZ_GF<3, 0b011000, (outs GPR:$rz), (ins sFPR64Op:$vrx),
158 def FMTVRL_D : F_XZ_FG<3, 0b011011, (outs sFPR64Op:$vrz), (ins GPR:$rx),
161 def FMTVRH_D : F_XZ_FG<3, 0b011010, (outs sFPR64Op:$vrz), (ins sFPR64Op:$vrZ, GPR:$rx),
168 def : Pat<(f32 (sint_to_fp GPR:$a)),
169 (FSITOS (COPY_TO_REGCLASS GPR:$a, sFPR32))>,
[all …]
H A DCSKYInstrAlias.td16 def : InstAlias<"bgeni16 $dst, $imm", (BGENI GPR:$dst, uimm5:$imm)>;
17 def : InstAlias<"bgeni32 $dst, $imm", (BGENI GPR:$dst, uimm5:$imm)>;
21 def : InstAlias<"grs\t$rz, $offset", (GRS32 GPR:$rz, bare_symbol:$offset)>;
31 def : InstAlias<"lrw $rz, $src", (PseudoLRW32 GPR:$rz, bare_symbol:$src)>;
32 def : InstAlias<"lrw $rz, $src", (LRW32 GPR:$rz, constpool_symbol:$src)>;
/openbsd-src/gnu/llvm/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td192 let MIOperandInfo = (ops GPR:$base, i32lo16s:$offset, AluOp:$Opcode);
204 let MIOperandInfo = (ops GPR:$Op1, GPR:$Op2, AluOp:$Opcode);
226 let MIOperandInfo = (ops GPR:$base, imm10:$offset, AluOp:$Opcode);
277 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
281 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
293 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
295 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
301 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
302 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
306 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMInstrInfo.td394 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
424 def top16Zero: PatLeaf<(i32 GPR:$src), [{
781 let MIOperandInfo = (ops GPR, i32imm);
792 let MIOperandInfo = (ops GPR, GPR, i32imm);
803 let MIOperandInfo = (ops GPR, i32imm);
1111 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
1132 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
1188 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
1189 // the GPR is purely vestigal at this point.
1210 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td80 let MIOperandInfo = (ops GPR, i16imm);
160 (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
176 (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
267 (outs GPR:$dst),
268 (ins GPR:$src2, GPR:$src),
270 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;
272 (outs GPR:$dst),
273 (ins GPR:$src2, i64imm:$imm),
275 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]>;
314 def NEG_64: NEG_RR<BPF_ALU64, BPF_NEG, (outs GPR:$dst), (ins GPR:$src),
[all …]
/openbsd-src/gnu/gcc/gcc/config/rs6000/
H A Dsync.md53 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
54 (unspec_volatile:GPR
55 [(match_operand:GPR 1 "memory_operand" "Z")] UNSPECV_LL))]
63 (set (match_operand:GPR 1 "memory_operand" "=Z")
64 (match_operand:GPR 2 "gpc_reg_operand" "r"))]
70 [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r")
71 (match_operand:GPR 1 "memory_operand" "+Z"))
73 (unspec:GPR
74 [(match_operand:GPR 2 "reg_or_short_operand" "rI")
75 (match_operand:GPR 3 "gpc_reg_operand" "r")]
[all …]
/openbsd-src/gnu/gcc/gcc/config/mips/
H A Dmips.md406 ;; This mode macro allows 32-bit and 64-bit GPR patterns to be generated
408 (define_mode_macro GPR [SI (DI "TARGET_64BIT")])
432 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
443 ;; Mode attributes for GPR loads and stores.
636 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
637 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
638 (match_operand:GPR 2 "arith_operand" "dI")])
662 [(set (match_operand:GPR 0 "register_operand")
663 (plus:GPR (match_operand:GPR 1 "register_operand")
664 (match_operand:GPR 2 "arith_operand")))]
[all …]
/openbsd-src/gnu/llvm/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_powerpc.h12 #define GPR_OFFSET(regname) (offsetof(GPR, regname))
13 #define FPR_OFFSET(regname) (sizeof(GPR) + offsetof(FPR, regname))
14 #define VMX_OFFSET(regname) (sizeof(GPR) + sizeof(FPR) + offsetof(VMX, regname))
15 #define GPR_SIZE(regname) (sizeof(((GPR *)NULL)->regname))
185 #define GPR GPR64 macro
187 #undef GPR
191 #define GPR GPR32 macro
193 #undef GPR
197 #define GPR GPR64 macro
202 (offsetof(GPR, regname) + (sizeof(((GPR *)NULL)->regname) - GPR_SIZE(reg)))
[all …]
H A DRegisterContextLinux_i386.cpp15 struct GPR { struct
61 GPR regs; // General purpose registers.
95 sizeof(((GPR *)nullptr)->orig_eax), in RegisterContextLinux_i386()
96 (LLVM_EXTENSION offsetof(GPR, orig_eax)), in RegisterContextLinux_i386()
107 size_t RegisterContextLinux_i386::GetGPRSizeStatic() { return sizeof(GPR); } in GetGPRSizeStatic()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64GenRegisterBankInfo.def28 // 6: GPR 32-bit value.
30 // 7: GPR 64-bit value.
32 // 8: GPR 128-bit value.
67 // 19: GPR 32-bit value.
71 // 22: GPR 64-bit value.
75 // 25: GPR 128-bit value. <-- This must match Last3OpsIdx.
80 // 28: FPR 16-bit value to GPR 16-bit. <-- This must match
85 // 30: FPR 32-bit value to GPR 32-bit value.
88 // 32: FPR 64-bit value to GPR 64-bit value.
91 // 34: FPR 128-bit value to GPR 128-bit value (invalid)
[all …]

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