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Searched refs:FSQRT (Results 1 – 25 of 51) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3538 { ISD::FSQRT, MVT::f32, { 3, 12, 1, 1 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3539 { ISD::FSQRT, MVT::v4f32, { 3, 12, 1, 1 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3540 { ISD::FSQRT, MVT::v8f32, { 6, 12, 1, 1 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3541 { ISD::FSQRT, MVT::v16f32, { 12, 20, 1, 3 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3542 { ISD::FSQRT, MVT::f64, { 6, 18, 1, 1 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3543 { ISD::FSQRT, MVT::v2f64, { 6, 18, 1, 1 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3544 { ISD::FSQRT, MVT::v4f64, { 12, 18, 1, 1 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3545 { ISD::FSQRT, MVT::v8f64, { 24, 32, 1, 3 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3654 { ISD::FSQRT, MVT::f32, { 7, 15, 1, 1 } }, // vsqrtss in getIntrinsicInstrCost()
3655 { ISD::FSQRT, MVT::v4f32, { 7, 15, 1, 1 } }, // vsqrtps in getIntrinsicInstrCost()
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H A DX86IntrinsicsInfo.h928 X86_INTRINSIC_DATA(avx512_sqrt_pd_512, INTR_TYPE_1OP, ISD::FSQRT, X86ISD::FSQRT_RND),
929 X86_INTRINSIC_DATA(avx512_sqrt_ps_512, INTR_TYPE_1OP, ISD::FSQRT, X86ISD::FSQRT_RND),
1208 X86_INTRINSIC_DATA(avx512fp16_sqrt_ph_512, INTR_TYPE_1OP, ISD::FSQRT, X86ISD::FSQRT_RND),
H A DX86.td541 // TuningFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
543 // vector FSQRT has higher throughput than the corresponding NR code.
/openbsd-src/usr.bin/awk/
H A Dawk.h146 #define FSQRT 2 macro
H A Dlex.c90 { "sqrt", FSQRT, BLTIN },
/openbsd-src/gnu/usr.bin/binutils-2.17/include/opcode/
H A Dm88k.h346 #define FSQRT NOP +5 macro
/openbsd-src/gnu/usr.bin/binutils/include/opcode/
H A Dm88k.h345 #define FSQRT NOP +5 macro
/openbsd-src/gnu/llvm/llvm/include/llvm/IR/
H A DConstrainedOps.def96 DAG_FUNCTION(sqrt, 1, 1, experimental_constrained_sqrt, FSQRT)
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h912 FSQRT, enumerator
H A DBasicTTIImpl.h516 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); in haveFastSqrt()
1768 ISD = ISD::FSQRT; in getTypeBasedIntrinsicInstrCost()
/openbsd-src/gnu/gcc/gcc/config/sh/
H A Dsh4a.md188 ;; Single-precision FDIV/FSQRT
H A Dsh4.md413 ;; Latency: 12/13 (FDIV); 11/12 (FSQRT)
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64SchedCyclone.td553 // FDIV,FSQRT
555 // TODO: Specialize FSQRT for longer latency.
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td122 defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>;
H A DMipsSEISelLowering.cpp148 setOperationAction(ISD::FSQRT, MVT::f16, Promote); in MipsSETargetLowering()
388 setOperationAction(ISD::FSQRT, Ty, Legal); in addMSAFloatType()
1912 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
H A DMipsInstrFPU.td543 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp199 case ISD::FSQRT: return "fsqrt"; in getOperationName()
H A DLegalizeFloatTypes.cpp125 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break; in SoftenFloatResult()
1266 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break; in ExpandFloatResult()
2273 case ISD::FSQRT: in PromoteFloatResult()
2639 case ISD::FSQRT: in SoftPromoteHalfResult()
H A DLegalizeVectorOps.cpp368 case ISD::FSQRT: in LegalizeOp()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h97 FSQRT, enumerator
H A DP9InstrResources.td1151 FSQRT
/openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td121 defm FSQRT : FT_XZ<0b011010, "fsqrt", UnOpFrag<(fsqrt node:$Src)>>;
/openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1863 setOperationAction(ISD::FSQRT, MVT::f128, Legal); in SparcTargetLowering()
1888 setOperationAction(ISD::FSQRT, MVT::f128, Custom); in SparcTargetLowering()
1940 setOperationAction(ISD::FSQRT, MVT::f32, Promote); in SparcTargetLowering()
3236 case ISD::FSQRT: return LowerF128Op(Op, DAG, in LowerOperation()
/openbsd-src/gnu/usr.bin/gcc/gcc/config/mmix/
H A Dmmix.md380 "FSQRT %0,%1")
/openbsd-src/gnu/gcc/gcc/config/mmix/
H A Dmmix.md434 "FSQRT %0,%1")

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