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Searched refs:FSHL (Results 1 – 19 of 19) sorted by relevance

/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h696 FSHL, enumerator
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3335 { ISD::FSHL, MVT::v8i64, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3336 { ISD::FSHL, MVT::v4i64, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3337 { ISD::FSHL, MVT::v2i64, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3338 { ISD::FSHL, MVT::v16i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3339 { ISD::FSHL, MVT::v8i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3340 { ISD::FSHL, MVT::v4i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3341 { ISD::FSHL, MVT::v32i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3342 { ISD::FSHL, MVT::v16i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3343 { ISD::FSHL, MVT::v8i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3891 { ISD::FSHL, MVT::i64, { 4, 4, 1, 4 } }, in getIntrinsicInstrCost()
[all …]
H A DX86ISelLowering.h39 FSHL, enumerator
H A DX86ISelLowering.cpp219 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering()
1201 setOperationAction(ISD::FSHL, VT, Custom); in X86TargetLowering()
1397 setOperationAction(ISD::FSHL, VT, Custom); in X86TargetLowering()
1836 setOperationAction(ISD::FSHL, MVT::v64i8, Custom); in X86TargetLowering()
1838 setOperationAction(ISD::FSHL, MVT::v32i16, Custom); in X86TargetLowering()
1840 setOperationAction(ISD::FSHL, MVT::v16i32, Custom); in X86TargetLowering()
1912 setOperationAction(ISD::FSHL, VT, Custom); in X86TargetLowering()
30987 assert((Op.getOpcode() == ISD::FSHL || Op.getOpcode() == ISD::FSHR) && in LowerFunnelShift()
31143 unsigned FSHOp = (IsFSHR ? X86ISD::FSHR : X86ISD::FSHL); in LowerFunnelShift()
31187 unsigned FunnelOpc = IsROTL ? ISD::FSHL : ISD::FSHR; in LowerRotate()
[all …]
H A DX86InstrInfo.td141 def X86fshl : SDNode<"X86ISD::FSHL", SDTIntShiftDOp>;
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp238 setOperationAction(ISD::FSHL, T, Custom); in initializeHVXLowering()
314 setOperationAction(ISD::FSHL, T, Custom); in initializeHVXLowering()
2075 assert(Opc == ISD::FSHL || Opc == ISD::FSHR); in LowerHvxFunnelShift()
2088 bool IsLeft = Opc == ISD::FSHL; in LowerHvxFunnelShift()
2122 unsigned MOpc = Opc == ISD::FSHL ? HexagonISD::MFSHL : HexagonISD::MFSHR; in LowerHvxFunnelShift()
3178 case ISD::FSHL: in LowerHvxOperation()
3218 case ISD::FSHL: in LowerHvxOperation()
H A DHexagonISelLowering.cpp1574 setOperationAction(ISD::FSHL, MVT::i32, Legal); in HexagonTargetLowering()
1575 setOperationAction(ISD::FSHL, MVT::i64, Legal); in HexagonTargetLowering()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp338 case ISD::FSHL: in LegalizeOp()
837 case ISD::FSHL: in Expand()
H A DSelectionDAGDumper.cpp260 case ISD::FSHL: return "fshl"; in getOperationName()
H A DLegalizeIntegerTypes.cpp274 case ISD::FSHL: in PromoteIntegerResult()
1688 case ISD::FSHL: in PromoteIntegerOperand()
2565 case ISD::FSHL: in ExpandIntegerResult()
4746 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR; in ExpandIntRes_Rotate()
4772 Opc == ISD::FSHL ? ISD::SETNE : ISD::SETEQ); in ExpandIntRes_FunnelShift()
H A DTargetLowering.cpp1969 case ISD::FSHL: in SimplifyDemandedBits()
1974 bool IsFSHL = (Op.getOpcode() == ISD::FSHL); in SimplifyDemandedBits()
4146 (N0.getOpcode() != ISD::FSHL && N0.getOpcode() != ISD::FSHR)) in foldSetCCWithFunnelShift()
7530 bool IsFSHL = Node->getOpcode() == ISD::FSHL; in expandFunnelShift()
7536 unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL; in expandFunnelShift()
7684 Tmp2 = DAG.getNode(ISD::FSHL, dl, VT, ShOpHi, ShOpLo, ShAmt); in expandShiftParts()
H A DDAGCombiner.cpp1739 case ISD::FSHL: in visit()
5401 if ((HandOpcode == ISD::FSHL || HandOpcode == ISD::FSHR) && in hoistLogicOpWithSameOpcodeHands()
7097 if (N0.getOpcode() == ISD::FSHL && N1.getOpcode() == ISD::SHL && in visitORCommutative()
7620 if (PosOpcode == ISD::FSHL && isPowerOf2_32(EltBits)) { in MatchFunnelPosNeg()
7633 TLI.isOperationLegalOrCustom(ISD::FSHL, VT)) { in MatchFunnelPosNeg()
7634 return DAG.getNode(ISD::FSHL, DL, VT, N0, N1.getOperand(0), Pos); in MatchFunnelPosNeg()
7672 bool HasFSHL = hasOperation(ISD::FSHL, VT); in MatchRotate()
7840 Res = DAG.getNode(UseFSHL ? ISD::FSHL : ISD::FSHR, DL, VT, LHSShiftArg, in MatchRotate()
7888 LExtOp0, RExtOp0, HasFSHL, ISD::FSHL, ISD::FSHR, DL); in MatchRotate()
7894 RExtOp0, LExtOp0, HasFSHR, ISD::FSHR, ISD::FSHL, DL); in MatchRotate()
[all …]
H A DLegalizeVectorTypes.cpp160 case ISD::FSHL: in ScalarizeVectorResult()
1122 case ISD::FSHL: in SplitVectorResult()
4131 case ISD::FSHL: in WidenVectorResult()
H A DSelectionDAG.cpp3339 case ISD::FSHL: in computeKnownBits()
3347 Known = computeKnownBits(Op.getOperand(Opcode == ISD::FSHL ? 0 : 1), in computeKnownBits()
3356 if (Opcode == ISD::FSHL) { in computeKnownBits()
4742 case ISD::FSHL: in canCreateUndefOrPoison()
H A DLegalizeDAG.cpp1260 case ISD::FSHL: in LegalizeOp()
3434 case ISD::FSHL: in ExpandNode()
H A DSelectionDAGBuilder.cpp6596 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR; in visitIntrinsicCall()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp807 ISD::FSHL, ISD::FSHR, in initActions()
/openbsd-src/gnu/llvm/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td403 def fshl : SDNode<"ISD::FSHL" , SDTIntShiftDOp>;
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp746 setOperationAction(ISD::FSHL, MVT::i64, Custom); in PPCTargetLowering()
749 setOperationAction(ISD::FSHL, MVT::i32, Custom); in PPCTargetLowering()
8925 bool IsFSHL = Op.getOpcode() == ISD::FSHL; in LowerFunnelShift()
11353 case ISD::FSHL: return LowerFunnelShift(Op, DAG); in LowerOperation()
11479 case ISD::FSHL: in ReplaceNodeResults()