| /openbsd-src/gnu/llvm/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 56 DAG_INSTRUCTION(FRem, 2, 1, experimental_constrained_frem, FREM)
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| /openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 394 FREM, enumerator
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| H A D | TargetLowering.h | 2723 case ISD::FREM: in isBinOp()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.h | 552 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); } in visitFRem()
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| H A D | SelectionDAGDumper.cpp | 273 case ISD::FREM: return "frem"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 115 case ISD::FREM: R = SoftenFloatRes_FREM(N); break; in SoftenFloatResult()
1277 case ISD::FREM: ExpandFloatRes_FREM(N, Lo, Hi); break; in ExpandFloatResult()
2286 case ISD::FREM: in PromoteFloatResult()
2652 case ISD::FREM: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 331 case ISD::FREM: in LegalizeOp()
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| H A D | FastISel.cpp | 1708 return selectBinaryOp(I, ISD::FREM); in selectOperator()
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| H A D | LegalizeVectorTypes.cpp | 142 case ISD::FREM: in ScalarizeVectorResult()
1105 case ISD::FREM: case ISD::VP_FREM: in SplitVectorResult()
3988 case ISD::FREM: in WidenVectorResult()
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| H A D | SelectionDAG.cpp | 4819 case ISD::FREM: in isKnownNeverNaN()
6014 case ISD::FREM: in foldConstantFPMath()
6052 case ISD::FREM: in foldConstantFPMath()
6245 case ISD::FREM: in getNode()
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| H A D | LegalizeDAG.cpp | 4218 case ISD::FREM: in ConvertNodeToLibcall()
4785 case ISD::FREM: in PromoteNode()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 120 ISD::FPOW, ISD::FREM, ISD::FCOPYSIGN}; in CSKYTargetLowering()
127 setOperationAction(ISD::FREM, VT, Expand); in CSKYTargetLowering()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetTransformInfo.cpp | 607 case ISD::FREM: in getArithmeticInstrCost()
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| H A D | AMDGPUISelLowering.cpp | 337 setOperationAction(ISD::FREM, {MVT::f16, MVT::f32, MVT::f64}, Custom); in AMDGPUTargetLowering()
449 ISD::FEXP, ISD::FLOG2, ISD::FREM, ISD::FLOG, in AMDGPUTargetLowering()
609 case ISD::FREM: in hasSourceMods()
1252 case ISD::FREM: return LowerFREM(Op, DAG); in LowerOperation()
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| H A D | AMDGPUISelDAGToDAG.cpp | 145 case ISD::FREM: in fp16SrcZerosHighBits()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1767 setOperationAction(ISD::FREM , MVT::f128, Expand); in SparcTargetLowering()
1772 setOperationAction(ISD::FREM , MVT::f64, Expand); in SparcTargetLowering()
1777 setOperationAction(ISD::FREM , MVT::f32, Expand); in SparcTargetLowering()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 149 setOperationAction(ISD::FREM, MVT::f32, Expand); in LoongArchTargetLowering()
165 setOperationAction(ISD::FREM, MVT::f64, Expand); in LoongArchTargetLowering()
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| /openbsd-src/gnu/usr.bin/gcc/gcc/config/mmix/ |
| H A D | mmix.md | 204 "FREM %0,%1,%2")
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| /openbsd-src/gnu/gcc/gcc/config/mmix/ |
| H A D | mmix.md | 258 "FREM %0,%1,%2")
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1819 case FRem: return ISD::FREM; in InstructionOpcodeToISD()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1589 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1634 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 433 setOperationAction(ISD::FREM, MVT::f32, Expand); in MipsTargetLowering()
434 setOperationAction(ISD::FREM, MVT::f64, Expand); in MipsTargetLowering()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 124 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 232 setOperationAction(ISD::FREM, VT, Expand); in initSPUActions()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 204 setOperationAction(ISD::FREM, VT, Expand); in addTypeForNEON()
364 setOperationAction(ISD::FREM, VT, Expand); in addMVEVectorTypes()
863 setOperationAction(ISD::FREM, MVT::v2f64, Expand); in ARMTargetLowering()
1039 setOperationAction(ISD::FREM, MVT::f64, Expand); in ARMTargetLowering()
1444 setOperationAction(ISD::FREM, MVT::f64, Expand); in ARMTargetLowering()
1445 setOperationAction(ISD::FREM, MVT::f32, Expand); in ARMTargetLowering()
1520 setOperationAction(ISD::FREM, MVT::f16, Promote); in ARMTargetLowering()
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