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Searched refs:FPR64 (Results 1 – 18 of 18) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchFloat64InstrInfo.td20 def FADD_D : FP_ALU_3R<0b00000001000000010, "fadd.d", FPR64>;
21 def FSUB_D : FP_ALU_3R<0b00000001000000110, "fsub.d", FPR64>;
22 def FMUL_D : FP_ALU_3R<0b00000001000001010, "fmul.d", FPR64>;
23 def FDIV_D : FP_ALU_3R<0b00000001000001110, "fdiv.d", FPR64>;
24 def FMADD_D : FP_ALU_4R<0b000010000010, "fmadd.d", FPR64>;
25 def FMSUB_D : FP_ALU_4R<0b000010000110, "fmsub.d", FPR64>;
26 def FNMADD_D : FP_ALU_4R<0b000010001010, "fnmadd.d", FPR64>;
27 def FNMSUB_D : FP_ALU_4R<0b000010001110, "fnmsub.d", FPR64>;
28 def FMAX_D : FP_ALU_3R<0b00000001000010010, "fmax.d", FPR64>;
29 def FMIN_D : FP_ALU_3R<0b00000001000010110, "fmin.d", FPR64>;
[all …]
H A DLoongArchRegisterInfo.td155 def FPR64 : RegisterClass<"LoongArch", [f64], 64, (sequence "F%u_64", 0, 31)>;
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoD.td60 def D : ExtInfo_r<DExt, FPR64>;
64 def DD : ExtInfo_rr<DExt, FPR64, FPR64>;
67 def DF : ExtInfo_rr<DExt, FPR64, FPR32>;
70 def DX : ExtInfo_rr<DExt, FPR64, GPR>;
73 def DX_64 : ExtInfo_rr<D64Ext, FPR64, GPR>;
74 def FD : ExtInfo_rr<DExt, FPR32, FPR64>;
77 def XD : ExtInfo_rr<DExt, GPR, FPR64>;
80 def XD_64 : ExtInfo_rr<D64Ext, GPR, FPR64>;
96 def FLD : FPLoad_r<0b011, "fld", FPR64, WriteFLD64>;
101 def FSD : FPStore_r<0b011, "fsd", FPR64, WriteFST64>;
[all …]
H A DRISCVInstrInfoZfh.td70 def DHmin : ExtInfo_rr<ZfhminDExt, FPR64, FPR16>;
72 def HDmin : ExtInfo_rr<ZfhminDExt, FPR16, FPR64>;
423 def : Pat<(any_fpround FPR64:$rs1), (FCVT_H_D FPR64:$rs1, 0b111)>;
427 def : Pat<(fcopysign FPR16:$rs1, FPR64:$rs2),
429 def : Pat<(fcopysign FPR64:$rs1, FPR16:$rs2), (FSGNJ_D $rs1, (FCVT_D_H $rs2))>;
H A DRISCVInstrInfoC.td505 def C_FLDSP : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000>,
565 def C_FSDSP : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000>,
882 def : CompressPat<(FLD FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm),
883 (C_FLDSP FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm)>;
924 def : CompressPat<(FSD FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm),
925 (C_FSDSP FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm)>;
H A DRISCVRegisterInfo.td252 def FPR64 : RegisterClass<"RISCV", [f64], 64, (add
H A DRISCVInstrInfoVPseudos.td133 def SCALAR_F64 : FPR_Info<FPR64, "F64", MxSet<64>.m, []>;
256 def VF64M1: VTypeInfo<vfloat64m1_t, vbool64_t, 64, VR, V_M1, f64, FPR64>;
275 VRM2, V_M2, f64, FPR64>;
277 VRM4, V_M4, f64, FPR64>;
279 VRM8, V_M8, f64, FPR64>;
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td1463 def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,
1466 (int_aarch64_fjcvtzs FPR64:$Rn))]> {
1722 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;
2814 // Match all load 64 bits width whose type is compatible with FPR64
2971 // Match all load 64 bits width whose type is compatible with FPR64
3160 // Match all load 64 bits width whose type is compatible with FPR64
3501 // Match all store 64 bits width whose type is compatible with FPR64
3504 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
3505 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
3506 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
[all …]
H A DAArch64InstrFormats.td4798 def UWDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR32, asm,
4799 [(set GPR32:$Rd, (OpN (f64 FPR64:$Rn)))]> {
4804 def UXDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR64, asm,
4805 [(set GPR64:$Rd, (OpN (f64 FPR64:$Rn)))]> {
4849 def SWDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR32,
4851 [(set GPR32:$Rd, (OpN (fmul FPR64:$Rn,
4858 def SXDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR64,
4860 [(set GPR64:$Rd, (OpN (fmul FPR64:$Rn,
4919 def UWDri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR64, f64, asm, node> {
4935 def UXDri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR64, f64, asm, node> {
[all …]
H A DAArch64InstrGISel.td262 def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),
263 (vector_extract (v2f32 FPR64:$Rn), (i64 1)))),
264 (f32 (FADDPv2i32p (v2f32 FPR64:$Rn)))>;
H A DAArch64RegisterInfo.td449 def FPR64 : RegisterClass<"AArch64", [f64, i64, v2f32, v1f64, v8i8, v4i16, v2i32,
455 64, (trunc FPR64, 16)>;
473 def DSeqPairs : RegisterTuples<[dsub0, dsub1], [(rotl FPR64, 0), (rotl FPR64, 1)]>;
475 [(rotl FPR64, 0), (rotl FPR64, 1),
476 (rotl FPR64, 2)]>;
478 [(rotl FPR64, 0), (rotl FPR64, 1),
479 (rotl FPR64, 2), (rotl FPR64, 3)]>;
520 def V64 : RegisterOperand<FPR64, "printVRegOperand"> {
653 defm VecListOne : VectorList<1, FPR64, FPR128>;
681 def FPR64Op : RegisterOperand<FPR64, "printOperand"> {
[all …]
H A DAArch64FrameLowering.cpp2502 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enumerator
2513 case FPR64: in getScale()
2572 RPI.Type = RegPairInfo::FPR64; in computeCalleeSaveRegisterPairs()
2594 case RegPairInfo::FPR64: in computeCalleeSaveRegisterPairs()
2770 case RegPairInfo::FPR64: in spillCalleeSavedRegisters()
2874 case RegPairInfo::FPR64: in restoreCalleeSavedRegisters()
H A DAArch64SVEInstrInfo.td762 def : Pat<(nxv2f64 (splat_vector (f64 FPR64:$src))),
763 (DUP_ZZI_D (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$src, dsub), 0)>;
2967 def : Pat<(nxv2i64 (vector_insert (nxv2i64 (undef)), (i64 FPR64:$src), 0)),
2968 (INSERT_SUBREG (nxv2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
2980 def : Pat<(nxv2f64 (vector_insert (nxv2f64 (undef)), (f64 FPR64:$src), 0)),
2981 (INSERT_SUBREG (nxv2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
2997 def : Pat<(nxv2f64 (vector_insert (nxv2f64 ZPR:$vec), (f64 FPR64:$src), 0)),
2998 (SEL_ZPZZ_D (PTRUE_D 1), (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$src, dsub), ZPR:$vec)>;
3057 def : Pat<(nxv2f64 (vector_insert (nxv2f64 ZPR:$vec), (f64 FPR64:$src), GPR64:$index)),
H A DSVEInstrFormats.td6530 def _D : sve_int_perm_clast_vz<0b11, ab, asm, ZPR64, FPR64>;
6634 def _D : sve_int_perm_last_v<0b11, ab, asm, ZPR64, FPR64>;
6836 def _D : sve_int_perm_cpy_v<0b11, asm, ZPR64, FPR64>;
6845 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn), 1>;
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td210 class FPR64<bits<16> num, string n, FPR32 high>
217 class FPR128<bits<16> num, string n, FPR64 low, FPR64 high>
227 def F#I#D : FPR64<I, "f"#I, !cast<FPR32>("F"#I#"S")>,
232 def F#I#D : FPR64<I, "v"#I, !cast<FPR32>("F"#I#"S")>,
237 def F#I#Q : FPR128<I, "f"#I, !cast<FPR64>("F"#!add(I, 2)#"D"),
238 !cast<FPR64>("F"#I#"D")>;
252 // A full 128-bit vector register, with an FPR64 as its high part.
253 class VR128<bits<16> num, string n, FPR64 high>
261 def V#I : VR128<I, "v"#I, !cast<FPR64>("F"#I#"D")>,
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp312 const auto &FPR64 = AArch64MCRegisterClasses[AArch64::FPR64RegClassID]; in isFpOrNEON() local
321 return FPR128.contains(Reg) || FPR64.contains(Reg) || FPR32.contains(Reg) || in isFpOrNEON()
/openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td196 def FPR64 : RegisterClass<"CSKY", [f64], 32,
H A DCSKYInstrInfoF2.td26 let MIOperandInfo = (ops FPR64, uimm5);
30 def FPR64Op : RegisterOperand<FPR64, "printFPR">;