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Searched refs:ExtOp (Results 1 – 18 of 18) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp4604 unsigned ExtOp, TruncOp; in PromoteNode() local
4606 ExtOp = ISD::BITCAST; in PromoteNode()
4613 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
4617 ExtOp = ISD::SIGN_EXTEND; in PromoteNode()
4621 ExtOp = ISD::ZERO_EXTEND; in PromoteNode()
4627 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); in PromoteNode()
4628 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); in PromoteNode()
4637 unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND in PromoteNode() local
4639 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); in PromoteNode()
4640 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); in PromoteNode()
[all …]
H A DDAGCombiner.cpp16344 unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND in FoldIntToFPToInt() local
16346 return DAG.getNode(ExtOp, SDLoc(N), VT, Src); in FoldIntToFPToInt()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp1535 MachineOperand ExtOp(EV); in insertInitializer() local
1546 .add(ExtOp); in insertInitializer()
1552 .add(ExtOp); in insertInitializer()
1557 .add(ExtOp) in insertInitializer()
1563 .add(ExtOp); in insertInitializer()
1571 .add(ExtOp) in insertInitializer()
1584 .add(ExtOp) in insertInitializer()
1589 .add(ExtOp); in insertInitializer()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstrSSE.td5051 SDNode ExtOp, SDNode InVecOp> {
5054 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
5063 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
5068 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
5077 def : Pat<(v16i16 (ExtOp (loadv16i8 addr:$src))),
5098 def : Pat<(v8i32 (ExtOp (loadv8i16 addr:$src))),
5108 def : Pat<(v4i64 (ExtOp (loadv4i32 addr:$src))),
5130 SDNode ExtOp> {
5132 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
5136 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
[all …]
H A DX86InstrAVX512.td10319 multiclass AVX512_pmovx_patterns_base<string OpcPrefix, SDNode ExtOp> {
10322 def : Pat<(v16i16 (ExtOp (loadv16i8 addr:$src))),
10327 def : Pat<(v8i32 (ExtOp (loadv8i16 addr:$src))),
10330 def : Pat<(v4i64 (ExtOp (loadv4i32 addr:$src))),
10336 def : Pat<(v32i16 (ExtOp (loadv32i8 addr:$src))),
10340 def : Pat<(v16i32 (ExtOp (loadv16i8 addr:$src))),
10342 def : Pat<(v16i32 (ExtOp (loadv16i16 addr:$src))),
10345 def : Pat<(v8i64 (ExtOp (loadv8i16 addr:$src))),
10348 def : Pat<(v8i64 (ExtOp (loadv8i32 addr:$src))),
10353 multiclass AVX512_pmovx_patterns<string OpcPrefix, SDNode ExtOp,
[all …]
H A DX86ISelLowering.cpp20254 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT, in InsertBitToMaskVector() local
20257 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp); in InsertBitToMaskVector()
42544 SDValue ExtOp = in SimplifyDemandedVectorEltsForTargetNode() local
42548 insertSubVector(UndefVec, ExtOp, 0, TLO.DAG, DL, ExtSizeInBits); in SimplifyDemandedVectorEltsForTargetNode()
42576 SDValue ExtOp = in SimplifyDemandedVectorEltsForTargetNode() local
42580 insertSubVector(UndefVec, ExtOp, 0, TLO.DAG, DL, ExtSizeInBits); in SimplifyDemandedVectorEltsForTargetNode()
42619 SDValue ExtOp = TLO.DAG.getNode(Opc, DL, ExtVT, Ops); in SimplifyDemandedVectorEltsForTargetNode() local
42622 insertSubVector(UndefVec, ExtOp, 0, TLO.DAG, DL, ExtSizeInBits); in SimplifyDemandedVectorEltsForTargetNode()
55887 unsigned ExtOp = DAG.getOpcode_EXTEND_VECTOR_INREG(InOpcode); in combineEXTRACT_SUBVECTOR() local
55888 return DAG.getNode(ExtOp, DL, VT, Ext); in combineEXTRACT_SUBVECTOR()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h1972 unsigned ExtOp = in getTypeBasedIntrinsicInstrCost() local
1977 Cost += 2 * thisT()->getCastInstrCost(ExtOp, ExtTy, RetTy, CCH, CostKind); in getTypeBasedIntrinsicInstrCost()
2039 unsigned ExtOp = IsSigned ? Instruction::SExt : Instruction::ZExt; in getTypeBasedIntrinsicInstrCost() local
2043 Cost += 2 * thisT()->getCastInstrCost(ExtOp, ExtTy, MulTy, CCH, CostKind); in getTypeBasedIntrinsicInstrCost()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUCodeGenPrepare.cpp435 Value *ExtOp = Builder.CreateZExt(I.getOperand(0), I32Ty); in promoteUniformBitreverseToI32() local
436 Value *ExtRes = Builder.CreateCall(I32, { ExtOp }); in promoteUniformBitreverseToI32()
H A DSIISelLowering.cpp10522 unsigned ExtOp = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in performIntMed3ImmCombine() local
10524 SDValue Tmp1 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(0)); in performIntMed3ImmCombine()
10525 SDValue Tmp2 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(1)); in performIntMed3ImmCombine()
10526 SDValue Tmp3 = DAG.getNode(ExtOp, SL, NVT, Op1); in performIntMed3ImmCombine()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMInstrNEON.td2996 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
3002 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3086 ValueType TyQ, ValueType TyD, SDNode OpNode, SDPatternOperator ExtOp,
3091 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
3092 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3099 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
3104 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3156 SDNode OpNode, SDPatternOperator ExtOp, bit Commutable>
3161 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3720 SDNode OpNode, SDPatternOperator ExtOp, bit Commutable = 0> {
[all …]
H A DARMISelLowering.cpp12650 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE; in AddCombineBUILD_VECTORToVPADDL() local
12651 return DAG.getNode(ExtOp, dl, VT, tmp); in AddCombineBUILD_VECTORToVPADDL()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp482 unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP); in buildBoolExt() local
483 return buildInstr(ExtOp, Res, Op); in buildBoolExt()
H A DLegalizerHelper.cpp1917 auto ExtOp = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {TruncOp}); in widenScalarAddSubOverflow() local
1919 MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, ExtOp); in widenScalarAddSubOverflow()
1993 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; in widenScalarMulo() local
1994 auto LeftOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {LHS}); in widenScalarMulo()
1995 auto RightOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {RHS}); in widenScalarMulo()
7294 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; in lowerSMULH_UMULH() local
7300 auto LHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(1)}); in lowerSMULH_UMULH()
7301 auto RHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(2)}); in lowerSMULH_UMULH()
/openbsd-src/gnu/llvm/llvm/lib/Transforms/Utils/
H A DSimplifyIndVar.cpp1488 Value *ExtOp = createExtendInst(Op, WideType, Cmp->isSigned(), Cmp); in widenLoopCompare() local
1489 DU.NarrowUse->replaceUsesOfWith(Op, ExtOp); in widenLoopCompare()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp6204 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4() local
6205 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_64SVR4()
14412 ConstantSDNode *ExtOp = dyn_cast<ConstantSDNode>(Extract.getOperand(1)); in combineBVOfVecSExt() local
14413 if (!ExtOp) in combineBVOfVecSExt()
14416 Index = ExtOp->getZExtValue(); in combineBVOfVecSExt()
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp6782 SDValue ExtOp = DAG.getNode(ExtOpcode, SDLoc(N), ExtVT, Op); in combineINT_TO_FP() local
6783 return DAG.getNode(Opcode, SDLoc(N), OutVT, ExtOp); in combineINT_TO_FP()
/openbsd-src/gnu/llvm/clang/lib/CodeGen/
H A DCGBuiltin.cpp7530 Value *ExtOp, Value *IndexOp, in packTBLDVectorList() argument
7534 if (ExtOp) in packTBLDVectorList()
7535 TblOps.push_back(ExtOp); in packTBLDVectorList()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp21053 SDValue ExtOp = Src->getOperand(0); in performSignExtendInRegCombine() local
21063 SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ExtOp.getValueType(), in performSignExtendInRegCombine()
21064 ExtOp, DAG.getValueType(ExtVT)); in performSignExtendInRegCombine()