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Searched refs:Enc (Results 1 – 25 of 29) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td17 class Wi<bits<16> Enc, string n> : Register<n> {
18 let HWEncoding = Enc;
24 class Ri<bits<16> Enc, string n, list<Register> subregs>
26 let HWEncoding = Enc;
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp387 auto Enc = getLitEncoding(Op, Desc.operands()[i], STI); in encodeInstruction() local
388 if (!Enc || *Enc != 255) in encodeInstruction()
459 auto Enc = getLitEncoding(MO, Desc.operands()[OpNo], STI); in getSDWASrcEncoding() local
460 if (Enc && *Enc != 255) { in getSDWASrcEncoding()
461 Op = *Enc | SDWA9EncValues::SRC_SGPR_MASK; in getSDWASrcEncoding()
493 uint64_t Enc = MRI.getEncodingValue(Reg); in getAVOperandEncoding() local
512 Enc |= 512; in getAVOperandEncoding()
514 Op = Enc; in getAVOperandEncoding()
582 if (auto Enc = getLitEncoding(MO, Desc.operands()[OpNo], STI)) { in getMachineOpValueCommon() local
583 Op = *Enc; in getMachineOpValueCommon()
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td29 class MipsReg<bits<16> Enc, string n> : Register<n> {
30 let HWEncoding = Enc;
34 class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
36 let HWEncoding = Enc;
41 class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>;
44 class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
45 : MipsRegWithSubRegs<Enc, n, subregs> {
50 class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
53 class AFPR<bits<16> Enc, string n, list<Register> subregs>
54 : MipsRegWithSubRegs<Enc, n, subregs> {
[all …]
/openbsd-src/gnu/llvm/llvm/include/llvm/Bitstream/
H A DBitCodes.h36 unsigned Enc : 3; // The encoding to use. variable
52 : Val(Data), IsLiteral(false), Enc(E) {} in Val()
61 Encoding getEncoding() const { assert(isEncoding()); return (Encoding)Enc; } in getEncoding()
/openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td13 class SparcReg<bits<16> Enc, string n> : Register<n> {
14 let HWEncoding = Enc;
18 class SparcCtrlReg<bits<16> Enc, string n>: Register<n> {
19 let HWEncoding = Enc;
32 class Ri<bits<16> Enc, string n> : SparcReg<Enc, n>;
35 class Rdi<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
41 class Rf<bits<16> Enc, string n> : SparcReg<Enc, n>;
44 class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
51 class Rq<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMMCInstLower.cpp159 int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm()); in LowerARMMachineInstrToMCInst() local
160 if (Enc != -1) in LowerARMMachineInstrToMCInst()
161 MCOp.setImm(Enc); in LowerARMMachineInstrToMCInst()
H A DARMRegisterInfo.td16 class ARMReg<bits<16> Enc, string n, list<Register> subregs = [],
18 let HWEncoding = Enc;
25 class ARMFReg<bits<16> Enc, string n> : Register<n> {
26 let HWEncoding = Enc;
/openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td14 class LoongArchReg<bits<16> Enc, string n, list<string> alt = []>
16 let HWEncoding = Enc;
20 class LoongArchReg32<bits<16> Enc, string n, list<string> alt = []>
22 let HWEncoding = Enc;
/openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td14 class CSKYReg<bits<6> Enc, string n, list<string> alt = []> : Register<n> {
15 let HWEncoding{5 - 0} = Enc;
19 class CSKYFReg32<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
20 let HWEncoding{4 - 0} = Enc;
/openbsd-src/gnu/llvm/clang/lib/CodeGen/
H A DTargetInfo.cpp10299 std::string Enc; member in __anon0040e4081b11::FieldEncoding
10301 FieldEncoding(bool b, SmallStringEnc &e) : HasName(b), Enc(e.c_str()) {} in FieldEncoding()
10302 StringRef str() { return Enc; } in str()
10305 return Enc < rhs.Enc; in operator <()
10488 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
10496 SmallStringEnc Enc; in emitTargetMD() local
10497 if (getTypeString(Enc, D, CGM, TSC)) { in emitTargetMD()
10500 llvm::MDString::get(Ctx, Enc.str())}; in emitTargetMD()
10642 static bool appendType(SmallStringEnc &Enc, QualType QType,
10654 SmallStringEnc Enc; in extractFieldType() local
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/openbsd-src/gnu/llvm/llvm/utils/TableGen/
H A DX86FoldTablesEmitter.cpp430 uint64_t Enc = getValueFromBitsInit(RegRec->getValueAsBitsInit("OpEncBits")); in addEntryWithFlags() local
437 } else if (Enc != X86Local::XOP && Enc != X86Local::VEX && in addEntryWithFlags()
438 Enc != X86Local::EVEX) { in addEntryWithFlags()
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td14 class RISCVReg<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
15 let HWEncoding{4-0} = Enc;
19 class RISCVReg16<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
20 let HWEncoding{4-0} = Enc;
45 class RISCVRegWithSubRegs<bits<5> Enc, string n, list<Register> subregs,
48 let HWEncoding{4-0} = Enc;
/openbsd-src/gnu/llvm/llvm/include/llvm/Transforms/IPO/
H A DAttributor.h579 IRPosition() : Enc(nullptr, ENC_VALUE) { verify(); }
665 return Enc == RHS.Enc && RHS.CBContext == CBContext;
908 operator void *() const { return Enc.getOpaqueValue(); }
914 Enc.setFromOpaqueValue(Ptr);
928 Enc = {&AnchorVal, ENC_FLOATING_FUNCTION};
930 Enc = {&AnchorVal, ENC_VALUE};
934 Enc = {&AnchorVal, ENC_VALUE};
938 Enc = {&AnchorVal, ENC_RETURNED_VALUE};
941 Enc = {&AnchorVal, ENC_VALUE};
976 Enc = {&U, ENC_CALL_SITE_ARGUMENT_USE};
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp5960 uint64_t Enc = (32 - *MaybeImmed) & 0x1f; in selectShiftA_32() local
5961 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}}; in selectShiftA_32()
5969 uint64_t Enc = 31 - *MaybeImmed; in selectShiftB_32() local
5970 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}}; in selectShiftB_32()
5978 uint64_t Enc = (64 - *MaybeImmed) & 0x3f; in selectShiftA_64() local
5979 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}}; in selectShiftA_64()
5987 uint64_t Enc = 63 - *MaybeImmed; in selectShiftB_64() local
5988 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}}; in selectShiftB_64()
6779 uint64_t Enc = AArch64_AM::encodeLogicalImmediate(CstVal, 32); in renderLogicalImm32() local
6780 MIB.addImm(Enc); in renderLogicalImm32()
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/openbsd-src/gnu/llvm/llvm/include/llvm/Demangle/
H A DItaniumDemangle.h2603 char Enc[2]; // Encoding member
2612 : Enc{E[0], E[1]}, Kind{K}, Flag{F}, Prec{P}, Name{N} {} in OperatorInfo()
2616 return *this < Other.Enc;
2619 return Enc[0] < Peek[0] || (Enc[0] == Peek[0] && Enc[1] < Peek[1]);
2622 return Enc[0] == Peek[0] && Enc[1] == Peek[1];
/openbsd-src/gnu/llvm/libcxxabi/src/demangle/
H A DItaniumDemangle.h2603 char Enc[2]; // Encoding member
2612 : Enc{E[0], E[1]}, Kind{K}, Flag{F}, Prec{P}, Name{N} {} in OperatorInfo()
2616 return *this < Other.Enc;
2619 return Enc[0] < Peek[0] || (Enc[0] == Peek[0] && Enc[1] < Peek[1]);
2622 return Enc[0] == Peek[0] && Enc[1] == Peek[1];
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp1389 unsigned Enc = 0; in getDefaultCustomOperandEncoding() local
1393 Enc |= Op.encode(Op.Default); in getDefaultCustomOperandEncoding()
1395 return Enc; in getDefaultCustomOperandEncoding()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp2632 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue()); in addModImmNotOperands() local
2633 Inst.addOperand(MCOperand::createImm(Enc)); in addModImmNotOperands()
2639 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue()); in addModImmNegOperands() local
2640 Inst.addOperand(MCOperand::createImm(Enc)); in addModImmNegOperands()
4461 unsigned Enc, unsigned Reg) { in insertNoDuplicates() argument
4462 Regs.emplace_back(Enc, Reg); in insertNoDuplicates()
4464 if (J->first == Enc) { in insertNoDuplicates()
4468 if (J->first < Enc) in insertNoDuplicates()
5491 int Enc = ARM_AM::getSOImmVal(Imm1); in parseModImm() local
5492 if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) { in parseModImm()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86RegisterInfo.td15 class X86Reg<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> {
17 let HWEncoding = Enc;
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIInsertWaitcnts.cpp1303 unsigned Enc = AMDGPU::encodeWaitcnt(IV, Wait); in generateWaitcnt() local
1305 BuildMI(Block, It, DL, TII->get(AMDGPU::S_WAITCNT)).addImm(Enc); in generateWaitcnt()
H A DBUFInstructions.td2658 class MUBUF_Real_Base_vi <bits<7> op, MUBUF_Pseudo ps, int Enc,
2662 SIMCInstr<ps.PseudoInstr, Enc>,
2925 class MTBUF_Real_Base_vi <bits<4> op, MTBUF_Pseudo ps, int Enc> :
2928 SIMCInstr<ps.PseudoInstr, Enc> {
/openbsd-src/gnu/usr.bin/perl/lib/unicore/
H A Dmktables.lst185 lib/Dt/Enc.pl
H A DPropValueAliases.txt605 dt ; Enc ; Circle ; enc
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp2270 if (unsigned Enc = dwarf::getAttributeEncoding(Token.stringValue())) { in parseDIExpression() local
2272 Elements.push_back(Enc); in parseDIExpression()
/openbsd-src/gnu/llvm/llvm/lib/Transforms/IPO/
H A DAttributor.cpp1190 assert(!Enc.getOpaqueValue() && in verify()

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