Searched refs:DivOpc (Results 1 – 6 of 6) sorted by relevance
| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1918 unsigned DivOpc; in selectDivRem() local
1924 DivOpc = Mips::SDIV; in selectDivRem()
1928 DivOpc = Mips::UDIV; in selectDivRem()
1937 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); in selectDivRem()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 1359 unsigned DivOpc = Node->getOpcode() == ISD::VP_SREM ? ISD::VP_SDIV : ISD::VP_UDIV; in ExpandVP_REM() local
1361 if (!TLI.isOperationLegalOrCustom(DivOpc, VT) || in ExpandVP_REM()
1374 SDValue Div = DAG.getNode(DivOpc, DL, VT, Dividend, Divisor, Mask, EVL); in ExpandVP_REM()
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| H A D | TargetLowering.cpp | 10182 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; in expandREM() local
10191 if (isOperationLegalOrCustom(DivOpc, VT)) { in expandREM()
10193 SDValue Divide = DAG.getNode(DivOpc, dl, VT, Dividend, Divisor); in expandREM()
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| /openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | BasicTTIImpl.h | 894 unsigned DivOpc = IsSigned ? Instruction::SDiv : Instruction::UDiv; variable
896 DivOpc, Ty, CostKind, Opd1Info, Opd2Info);
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 4572 unsigned DivOpc; in selectRem() local
4578 DivOpc = Is64bit ? AArch64::SDIVXr : AArch64::SDIVWr; in selectRem()
4581 DivOpc = Is64bit ? AArch64::UDIVXr : AArch64::UDIVWr; in selectRem()
4595 Register QuotReg = fastEmitInst_rr(DivOpc, RC, Src0Reg, Src1Reg); in selectRem()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 4865 unsigned DivOpc = IsSigned ? ISD::SDIV : ISD::UDIV; in PerformREMCombine() local
4871 if (U->getOpcode() == DivOpc && U->getOperand(0) == Num && in PerformREMCombine()
4876 DAG.getNode(DivOpc, DL, VT, Num, Den), in PerformREMCombine()
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