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Searched refs:DestReg (Results 1 – 25 of 129) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp63 const DebugLoc &dl, unsigned DestReg, in emitThumb1LoadConstPool() argument
76 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
83 const DebugLoc &dl, unsigned DestReg, in emitThumb2LoadConstPool() argument
95 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
110 assert((isARMLowRegister(DestReg) || DestReg.isVirtual()) && in emitLoadConstPool()
112 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
115 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
125 const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, in emitThumbRegPlusImmInReg() argument
130 bool isHigh = !isARMLowRegister(DestReg) || in emitThumbRegPlusImmInReg()
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H A DThumb1InstrInfo.cpp41 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
51 || !ARM::tGPRRegClass.contains(DestReg)) in copyPhysReg()
52 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
62 BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg) in copyPhysReg()
74 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
109 Register DestReg, int FI, in loadRegFromStackSlot() argument
114 (DestReg.isPhysical() && isARMLowRegister(DestReg))) && in loadRegFromStackSlot()
118 (DestReg.isPhysical() && isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
127 BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) in loadRegFromStackSlot()
H A DThumb2InstrInfo.cpp134 Register DestReg = MI.getOperand(0).getReg(); in optimizeSelect() local
136 if (!DestReg.isVirtual()) in optimizeSelect()
140 get(ARM::t2CSEL), DestReg) in optimizeSelect()
152 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
155 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
156 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); in copyPhysReg()
158 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
210 Register DestReg, int FI, in loadRegFromStackSlot() argument
223 BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) in loadRegFromStackSlot()
235 if (DestReg.isVirtual()) { in loadRegFromStackSlot()
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/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZPostRewrite.cpp82 Register DestReg = MBBI->getOperand(0).getReg(); in selectLOCRMux() local
84 bool DestIsHigh = SystemZ::isHighReg(DestReg); in selectLOCRMux()
103 Register DestReg = MBBI->getOperand(0).getReg(); in selectSELRMux() local
106 bool DestIsHigh = SystemZ::isHighReg(DestReg); in selectSELRMux()
113 if (DestReg != Src1Reg && DestReg != Src2Reg) { in selectSELRMux()
116 TII->get(SystemZ::COPY), DestReg) in selectSELRMux()
118 MBBI->getOperand(1).setReg(DestReg); in selectSELRMux()
119 Src1Reg = DestReg; in selectSELRMux()
123 TII->get(SystemZ::COPY), DestReg) in selectSELRMux()
125 MBBI->getOperand(2).setReg(DestReg); in selectSELRMux()
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/openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp437 Register DestReg, int FI, in loadRegFromStackSlot() argument
472 BuildMI(MBB, I, DL, get(Opcode), DestReg) in loadRegFromStackSlot()
480 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
483 CSKY::CARRYRegClass.contains(DestReg)) { in copyPhysReg()
485 BuildMI(MBB, I, DL, get(CSKY::BTSTI32), DestReg) in copyPhysReg()
490 BuildMI(MBB, I, DL, get(CSKY::BTSTI16), DestReg) in copyPhysReg()
498 CSKY::GPRRegClass.contains(DestReg)) { in copyPhysReg()
501 BuildMI(MBB, I, DL, get(CSKY::MVC32), DestReg) in copyPhysReg()
504 assert(DestReg < CSKY::R16); in copyPhysReg()
505 assert(DestReg < CSKY::R8); in copyPhysReg()
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/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp221 Register DestReg = MI.getOperand(0).getReg(); in doAtomicBinOpExpansion() local
233 BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg) in doAtomicBinOpExpansion()
240 .addReg(DestReg) in doAtomicBinOpExpansion()
257 MachineBasicBlock *MBB, Register DestReg, in insertMaskedMerge() argument
273 BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg) in insertMaskedMerge()
283 Register DestReg = MI.getOperand(0).getReg(); in doMaskedAtomicBinOpExpansion() local
299 BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg) in doMaskedAtomicBinOpExpansion()
311 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
316 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
321 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
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H A DRISCVMergeBaseOffset.cpp286 Register DestReg = Lo.getOperand(0).getReg(); in detectAndFoldOffset() local
291 if (!MRI->hasOneUse(DestReg)) in detectAndFoldOffset()
295 MachineInstr &Tail = *MRI->use_instr_begin(DestReg); in detectAndFoldOffset()
331 return foldLargeOffset(Hi, Lo, Tail, DestReg); in detectAndFoldOffset()
338 return foldShiftedOffset(Hi, Lo, Tail, DestReg); in detectAndFoldOffset()
346 Register DestReg = Lo.getOperand(0).getReg(); in foldIntoMemoryOps() local
361 for (const MachineInstr &UseMI : MRI->use_instructions(DestReg)) { in foldIntoMemoryOps()
386 if (DestReg == UseMI.getOperand(0).getReg()) in foldIntoMemoryOps()
388 assert(DestReg == UseMI.getOperand(1).getReg() && in foldIntoMemoryOps()
418 llvm::make_early_inc_range(MRI->use_instructions(DestReg))) { in foldIntoMemoryOps()
H A DRISCVRegisterInfo.cpp166 const DebugLoc &DL, Register DestReg, in adjustReg() argument
171 if (DestReg == SrcReg && !Offset.getFixed() && !Offset.getScalable()) in adjustReg()
189 Register ScratchReg = DestReg; in adjustReg()
190 if (DestReg == SrcReg) in adjustReg()
193 BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), DestReg) in adjustReg()
196 SrcReg = DestReg; in adjustReg()
201 if (DestReg == SrcReg && Val == 0) in adjustReg()
207 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
225 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
229 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
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/openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchExpandAtomicPseudoInsts.cpp152 Register DestReg = MI.getOperand(0).getReg(); in doAtomicBinOpExpansion() local
169 TII->get(Width == 32 ? LoongArch::LL_W : LoongArch::LL_D), DestReg) in doAtomicBinOpExpansion()
182 .addReg(DestReg) in doAtomicBinOpExpansion()
190 .addReg(DestReg) in doAtomicBinOpExpansion()
195 .addReg(DestReg) in doAtomicBinOpExpansion()
200 .addReg(DestReg) in doAtomicBinOpExpansion()
205 .addReg(DestReg) in doAtomicBinOpExpansion()
210 .addReg(DestReg) in doAtomicBinOpExpansion()
225 MachineBasicBlock *MBB, Register DestReg, in insertMaskedMerge() argument
239 BuildMI(MBB, DL, TII->get(LoongArch::XOR), DestReg) in insertMaskedMerge()
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/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp411 Register DestReg = I->getOperand(0).getReg(); in searchALUInst() local
423 if (Opnd.getReg() == DestReg) { in searchALUInst()
444 if (TRI->regsOverlap(DestReg, Opnd.getReg())) in searchALUInst()
572 Register DestReg = MI.getOperand(0).getReg(); in optTwoAddrLEA() local
577 if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP)) in optTwoAddrLEA()
594 (DestReg == BaseReg || DestReg == IndexReg)) { in optTwoAddrLEA()
596 if (DestReg != BaseReg) in optTwoAddrLEA()
601 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
606 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
609 } else if (DestReg == BaseReg && IndexReg == 0) { in optTwoAddrLEA()
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/openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/AsmParser/
H A DLoongArchAsmParser.cpp88 void emitLAInstSeq(MCRegister DestReg, MCRegister TmpReg,
757 void LoongArchAsmParser::emitLAInstSeq(MCRegister DestReg, MCRegister TmpReg, in emitLAInstSeq() argument
771 Out.emitInstruction(MCInstBuilder(Opc).addReg(DestReg).addExpr(LE), in emitLAInstSeq()
780 MCInstBuilder(Opc).addReg(DestReg).addReg(DestReg).addImm(0), in emitLAInstSeq()
785 MCInstBuilder(Opc).addReg(DestReg).addReg(DestReg).addExpr(LE), in emitLAInstSeq()
791 .addReg(DestReg == TmpReg ? DestReg : TmpReg) in emitLAInstSeq()
792 .addReg(DestReg == TmpReg ? DestReg : TmpReg) in emitLAInstSeq()
805 .addReg(DestReg == TmpReg ? TmpReg : LoongArch::R0) in emitLAInstSeq()
812 MCInstBuilder(Opc).addReg(DestReg).addReg(DestReg).addReg(TmpReg), in emitLAInstSeq()
829 MCRegister DestReg = Inst.getOperand(0).getReg(); in emitLoadAddressAbs() local
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/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp180 bool emitCmp(unsigned DestReg, const CmpInst *CI);
184 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
187 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
189 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
191 unsigned DestReg);
193 unsigned DestReg);
390 Register DestReg = createResultReg(RC); in materializeFP() local
392 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
393 return DestReg; in materializeFP()
396 Register DestReg = createResultReg(RC); in materializeFP() local
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H A DMipsSEInstrInfo.cpp85 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
90 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
111 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) in copyPhysReg()
119 if (Mips::CCRRegClass.contains(DestReg)) in copyPhysReg()
121 else if (Mips::FGR32RegClass.contains(DestReg)) in copyPhysReg()
123 else if (Mips::HI32RegClass.contains(DestReg)) in copyPhysReg()
124 Opc = Mips::MTHI, DestReg = 0; in copyPhysReg()
125 else if (Mips::LO32RegClass.contains(DestReg)) in copyPhysReg()
126 Opc = Mips::MTLO, DestReg = 0; in copyPhysReg()
127 else if (Mips::HI32DSPRegClass.contains(DestReg)) in copyPhysReg()
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/openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp409 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
423 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
424 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
426 else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
431 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
432 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
434 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
436 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
444 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
447 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp266 Register DestReg = MI->getOperand(0).getReg(); in getAluKind() local
267 if (regBelongsToClass(DestReg, &R600::R600_TReg32_XRegClass) || in getAluKind()
268 regBelongsToClass(DestReg, &R600::R600_AddrRegClass)) in getAluKind()
270 if (regBelongsToClass(DestReg, &R600::R600_TReg32_YRegClass)) in getAluKind()
272 if (regBelongsToClass(DestReg, &R600::R600_TReg32_ZRegClass)) in getAluKind()
274 if (regBelongsToClass(DestReg, &R600::R600_TReg32_WRegClass)) in getAluKind()
276 if (regBelongsToClass(DestReg, &R600::R600_Reg128RegClass)) in getAluKind()
353 Register DestReg = MI->getOperand(DstIndex).getReg(); in AssignSlot() local
360 MO.getReg() == DestReg) in AssignSlot()
366 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_XRegClass); in AssignSlot()
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H A DAMDGPUMachineCFGStructurizer.cpp43 unsigned DestReg;
58 PHIInfoElementT *findPHIInfoElement(unsigned DestReg);
65 void addDest(unsigned DestReg, const DebugLoc &DL);
67 void deleteDef(unsigned DestReg);
68 void addSource(unsigned DestReg, unsigned SourceReg,
70 void removeSource(unsigned DestReg, unsigned SourceReg,
73 unsigned &DestReg);
75 unsigned getNumSources(unsigned DestReg);
112 return Info->DestReg; in phiInfoElementGetDest()
117 Info->DestReg = NewDef; in phiInfoElementSetDef()
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/openbsd-src/gnu/llvm/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp146 inline MachineInstrBuilder build(const MCInstrDesc &MCID, Register DestReg) { in build() argument
147 return BuildMI(MBB, II, DL, MCID, DestReg); in build()
149 inline MachineInstrBuilder build(unsigned InstOpc, Register DestReg) { in build() argument
150 return build(get(InstOpc), DestReg); in build()
264 Register DestReg = MI.getOperand(0).getReg(); in processLDQ() local
265 Register DestHiReg = getSubReg(DestReg, VE::sub_even); in processLDQ()
266 Register DestLoReg = getSubReg(DestReg, VE::sub_odd); in processLDQ()
334 Register DestReg = MI.getOperand(0).getReg(); in processLDVM() local
352 build(VE::LVMir, DestReg).addImm(i).addReg(TmpReg, getKillRegState(true)); in processLDVM()
354 build(VE::LVMir_m, DestReg) in processLDVM()
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H A DVEInstrInfo.cpp328 MCRegister DestReg, MCRegister SrcReg, bool KillSrc, in copyPhysSubRegs() argument
335 Register SubDest = TRI->getSubReg(DestReg, SubRegIdx[Idx]); in copyPhysSubRegs()
354 MovMI->addRegisterDefined(DestReg, TRI); in copyPhysSubRegs()
361 MCRegister DestReg, MCRegister SrcReg, in copyPhysReg() argument
364 if (IsAliasOfSX(SrcReg) && IsAliasOfSX(DestReg)) { in copyPhysReg()
365 BuildMI(MBB, I, DL, get(VE::ORri), DestReg) in copyPhysReg()
368 } else if (VE::V64RegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
382 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(VE::VORmvl), DestReg) in copyPhysReg()
387 } else if (VE::VMRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
388 BuildMI(MBB, I, DL, get(VE::ANDMmm), DestReg) in copyPhysReg()
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/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonSplitConst32AndConst64.cpp77 Register DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
80 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestReg) in runOnMachineFunction()
84 Register DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
87 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo); in runOnMachineFunction()
88 Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi); in runOnMachineFunction()
/openbsd-src/gnu/llvm/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp33 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
35 if (BPF::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
36 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg) in copyPhysReg()
38 else if (BPF::GPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
39 BuildMI(MBB, I, DL, get(BPF::MOV_rr_32), DestReg) in copyPhysReg()
150 Register DestReg, int FI, in loadRegFromStackSlot() argument
159 BuildMI(MBB, I, DL, get(BPF::LDD), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
161 BuildMI(MBB, I, DL, get(BPF::LDW32), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
/openbsd-src/gnu/llvm/llvm/lib/Target/AVR/
H A DAVRInstrInfo.cpp43 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
49 if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
52 if (STI.hasMOVW() && AVR::DREGSMOVWRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
53 BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg) in copyPhysReg()
58 TRI.splitReg(DestReg, DestLo, DestHi); in copyPhysReg()
74 if (AVR::GPR8RegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
76 } else if (SrcReg == AVR::SP && AVR::DREGSRegClass.contains(DestReg)) { in copyPhysReg()
78 } else if (DestReg == AVR::SP && AVR::DREGSRegClass.contains(SrcReg)) { in copyPhysReg()
84 BuildMI(MBB, MI, DL, get(Opc), DestReg) in copyPhysReg()
161 Register DestReg, int FrameIndex, in loadRegFromStackSlot() argument
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/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp614 Register DestReg = MI->getOperand(0).getReg(); in scanInstruction() local
617 << printReg(DestReg, TRI) << " at " << *MI); in scanInstruction()
619 auto G = std::make_unique<Chain>(MI, Idx, getColor(DestReg)); in scanInstruction()
620 ActiveChains[DestReg] = G.get(); in scanInstruction()
627 Register DestReg = MI->getOperand(0).getReg(); in scanInstruction() local
632 if (DestReg != AccumReg) in scanInstruction()
647 ActiveChains[AccumReg]->add(MI, Idx, getColor(DestReg)); in scanInstruction()
649 if (DestReg != AccumReg) { in scanInstruction()
650 ActiveChains[DestReg] = ActiveChains[AccumReg]; in scanInstruction()
663 << printReg(DestReg, TRI) << "\n"); in scanInstruction()
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/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h366 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
369 .addReg(DestReg, RegState::Define); in BuildMI()
378 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
384 .addReg(DestReg, RegState::Define); in BuildMI()
396 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
402 .addReg(DestReg, RegState::Define); in BuildMI()
407 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
412 DestReg); in BuildMI()
413 return BuildMI(BB, MachineBasicBlock::iterator(I), MIMD, MCID, DestReg); in BuildMI()
418 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
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/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInfo.cpp59 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
65 Register::isVirtualRegister(DestReg) in copyPhysReg()
66 ? MRI.getRegClass(DestReg) in copyPhysReg()
67 : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg); in copyPhysReg()
71 BuildMI(MBB, I, DL, get(CopyOpcode), DestReg) in copyPhysReg()
/openbsd-src/gnu/llvm/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp64 Register DestReg, int FrameIdx, in loadRegFromStackSlot() argument
80 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
84 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
92 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
95 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
97 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
102 BuildMI(MBB, I, DL, get(Opc), DestReg) in copyPhysReg()

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