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Searched refs:DefIdx (Results 1 – 25 of 45) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/include/llvm/MC/
H A DMCInstrItineraries.h184 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding() argument
188 if ((FirstDefIdx + DefIdx) >= LastDefIdx) in hasPipelineForwarding()
190 if (Forwardings[FirstDefIdx + DefIdx] == 0) in hasPipelineForwarding()
198 return Forwardings[FirstDefIdx + DefIdx] == in hasPipelineForwarding()
205 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency() argument
210 int DefCycle = getOperandCycle(DefClass, DefIdx); in getOperandLatency()
220 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
H A DMCSubtargetInfo.h177 unsigned DefIdx) const { in getWriteLatencyEntry() argument
178 assert(DefIdx < SC->NumWriteLatencyEntries && in getWriteLatencyEntry()
181 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx]; in getWriteLatencyEntry()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DTargetSchedule.cpp142 unsigned DefIdx = 0; in findDefIdx() local
146 ++DefIdx; in findDefIdx()
148 return DefIdx; in findDefIdx()
202 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
203 if (DefIdx < SCDesc->NumWriteLatencyEntries) { in computeOperandLatency()
206 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeOperandLatency()
228 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for " in computeOperandLatency()
H A DLiveIntervalCalc.cpp36 SlotIndex DefIdx = in createDeadDef() local
40 LR.createDeadDef(DefIdx, Alloc); in createDeadDef()
181 unsigned DefIdx; in extendToUses() local
184 else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) { in extendToUses()
187 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber(); in extendToUses()
H A DTargetInstrInfo.cpp1223 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
1233 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
1235 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1297 unsigned DefIdx) const { in hasLowDefLatency()
1303 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
1392 unsigned DefIdx, in getOperandLatency() argument
1397 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1401 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceInputs() argument
1407 return getRegSequenceLikeInputs(MI, DefIdx, InputRegs); in getRegSequenceInputs()
1411 assert(DefIdx == 0 && "REG_SEQUENCE only has one def"); in getRegSequenceInputs()
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H A DPeepholeOptimizer.cpp372 unsigned DefIdx = 0; member in __anon629c1d000111::ValueTracker
426 DefIdx = MRI.def_begin(Reg).getOperandNo(); in ValueTracker()
1831 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromCopy()
1852 const MachineOperand DefOp = Def->getOperand(DefIdx); in getNextSourceFromBitcast()
1859 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx; in getNextSourceFromBitcast()
1896 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromRegSequence()
1919 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs)) in getNextSourceFromRegSequence()
1940 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromInsertSubreg()
1953 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg)) in getNextSourceFromInsertSubreg()
1969 const MachineOperand &MODef = Def->getOperand(DefIdx); in getNextSourceFromInsertSubreg()
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H A DMachineVerifier.cpp260 SlotIndex DefIdx, const LiveRange &LR,
2096 unsigned DefIdx; in visitMachineOperand() local
2099 MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) && in visitMachineOperand()
2100 Reg != MI->getOperand(DefIdx).getReg()) in visitMachineOperand()
2338 unsigned MONum, SlotIndex DefIdx, in checkLivenessAtDef() argument
2343 if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) { in checkLivenessAtDef()
2352 if (((SubRangeCheck || MO->getSubReg() == 0) && VNI->def != DefIdx) || in checkLivenessAtDef()
2353 !SlotIndex::isSameInstr(VNI->def, DefIdx) || in checkLivenessAtDef()
2354 (VNI->def != DefIdx && in checkLivenessAtDef()
2355 (!VNI->def.isEarlyClobber() || !DefIdx.isRegister()))) { in checkLivenessAtDef()
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H A DLiveRangeEdit.cpp167 SlotIndex DefIdx; in canRematerializeAt() local
169 DefIdx = LIS.getInstructionIndex(*RM.OrigMI); in canRematerializeAt()
176 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
H A DMachineInstr.cpp265 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand() local
266 if (DefIdx != -1) in addOperand()
267 tieOperands(DefIdx, OpNo); in addOperand()
903 unsigned DefIdx; in getRegClassConstraint() local
904 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
905 OpIdx = DefIdx; in getRegClassConstraint()
1107 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands() argument
1108 MachineOperand &DefMO = getOperand(DefIdx); in tieOperands()
1115 if (DefIdx < TiedMax) in tieOperands()
1116 UseMO.TiedTo = DefIdx + 1; in tieOperands()
H A DRenameIndependentSubregs.cpp335 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef); in computeMainRangesFixFlags() local
336 SlotIndex RegDefIdx = DefIdx.getRegSlot(); in computeMainRangesFixFlags()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h542 unsigned DefIdx = 0; in getDefIndex() local
546 ++DefIdx; in getDefIndex()
549 return DefIdx; in getDefIndex()
792 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { in tryCombineUnmergeDefs() local
793 Register DefReg = MI.getReg(DefIdx); in tryCombineUnmergeDefs()
795 DeadDefs[DefIdx] = true; in tryCombineUnmergeDefs()
808 MI.getOperand(DefIdx).setReg(DefReg); in tryCombineUnmergeDefs()
810 DeadDefs[DefIdx] = true; in tryCombineUnmergeDefs()
1042 for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs; in tryCombineUnmergeValues() local
1043 ++j, ++DefIdx) in tryCombineUnmergeValues()
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/openbsd-src/gnu/llvm/llvm/lib/MC/
H A DMCSchedule.cpp44 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
45 DefIdx != DefEnd; ++DefIdx) { in computeInstrLatency()
48 STI.getWriteLatencyEntry(&SCDesc, DefIdx); in computeInstrLatency()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h61 const MachineInstr &MI, unsigned DefIdx,
74 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
90 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
320 const MachineInstr &DefMI, unsigned DefIdx,
324 SDNode *DefNode, unsigned DefIdx,
427 unsigned DefIdx, unsigned DefAlign) const;
431 unsigned DefIdx, unsigned DefAlign) const;
442 unsigned DefIdx, unsigned DefAlign,
447 const MachineInstr &DefMI, unsigned DefIdx,
464 const MachineInstr &DefMI, unsigned DefIdx,
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H A DARMBaseInstrInfo.cpp3892 unsigned DefIdx, unsigned DefAlign) const { in getVLDMDefCycle() argument
3893 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getVLDMDefCycle()
3896 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
3933 unsigned DefIdx, unsigned DefAlign) const { in getLDMDefCycle() argument
3934 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getLDMDefCycle()
3937 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
4036 unsigned DefIdx, unsigned DefAlign, in getOperandLatency() argument
4042 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) in getOperandLatency()
4043 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
4052 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
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/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp623 int DefIdx = SwapMap[DefMI]; in formWebs() local
624 (void)EC->unionSets(SwapVector[DefIdx].VSEId, in formWebs()
628 SwapVector[DefIdx].VSEId, in formWebs()
727 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
729 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad || in recordUnoptimizableWebs()
730 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
736 LLVM_DEBUG(dbgs() << " def " << DefIdx << ": "); in recordUnoptimizableWebs()
803 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
804 SwapVector[DefIdx].WillRemove = 1; in markSwapsForRemoval()
H A DPPCInstrInfo.h442 const MachineInstr &DefMI, unsigned DefIdx,
446 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
448 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
454 unsigned DefIdx) const override { in hasLowDefLatency() argument
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h539 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
557 bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
577 bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
1294 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs() argument
1308 unsigned DefIdx, in getExtractSubregLikeInputs() argument
1322 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, in getInsertSubregLikeInputs() argument
1655 SDNode *DefNode, unsigned DefIdx,
1667 const MachineInstr &DefMI, unsigned DefIdx,
1697 const MachineInstr &DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
1707 unsigned DefIdx) const;
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp403 int DefIdx = mapRegToGPRIndex(MI.getOperand(0).getReg()); in handleADRP() local
406 if (DefIdx != OpIdx && (DefInfo.OneUser || DefInfo.MultiUsers)) in handleADRP()
571 int DefIdx = mapRegToGPRIndex(Def.getReg()); in runOnMachineFunction() local
573 if (DefIdx >= 0 && OpIdx >= 0 && in runOnMachineFunction()
574 handleMiddleInst(MI, LOHInfos[DefIdx], LOHInfos[OpIdx])) in runOnMachineFunction()
/openbsd-src/gnu/llvm/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp217 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; in getLatency() local
218 DefIdx != DefEnd; ++DefIdx) { in getLatency()
221 DefIdx); in getLatency()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.h141 unsigned DefIdx = 0; variable
160 return DefIdx-1; in GetIdx()
H A DScheduleDAGSDNodes.cpp478 unsigned DefIdx = N->getOperand(i).getResNo(); in AddSchedEdges() local
515 ST.adjustSchedDependency(OpSU, DefIdx, &SU, i, Dep); in AddSchedEdges()
578 DefIdx = 0; in InitNodeNumDefs()
592 for (;DefIdx < NodeNumDefs; ++DefIdx) { in Advance()
593 if (!Node->hasAnyUseOfValue(DefIdx)) in Advance()
595 ValueType = Node->getSimpleValueType(DefIdx); in Advance()
596 ++DefIdx; in Advance()
658 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency() local
662 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in computeOperandLatency()
/openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp210 unsigned DefIdx = 0; in tryInlineAsm() local
214 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx)) in tryInlineAsm()
215 IsTiedToChangedOp = OpChanged[DefIdx]; in tryInlineAsm()
301 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx); in tryInlineAsm()
/openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp162 unsigned DefIdx = 0; in selectInlineAsm() local
166 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx)) in selectInlineAsm()
167 IsTiedToChangedOp = OpChanged[DefIdx]; in selectInlineAsm()
252 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx); in selectInlineAsm()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp563 int DefIdx = -1; in restoreLatency() local
575 DefIdx = OpNum; in restoreLatency()
578 assert(DefIdx >= 0 && "Def Reg not found in Src MI"); in restoreLatency()
585 DefIdx, *DstI, OpNum)); in restoreLatency()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp435 unsigned DefIdx = OpInfo.getMatchedOperand(); in lowerInlineAsm() local
438 for (unsigned i = 0; i < DefIdx; ++i) in lowerInlineAsm()
472 unsigned Flag = InlineAsm::getFlagWordForMatchingOp(UseFlag, DefIdx); in lowerInlineAsm()

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