| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | MIMGInstructions.td | 348 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
361 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
372 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask,
385 (ins SReg_256:$srsrc, DMask:$dmask,
397 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask,
410 (ins SReg_256:$srsrc, DMask:$dmask,
516 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
530 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
542 DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
555 (ins SReg_256:$srsrc, DMask:$dmask,
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| H A D | SILoadStoreOptimizer.cpp | 115 unsigned DMask; member
180 return (InstClass == MIMG) ? DMask < Other.DMask : Offset < Other.Offset; in operator <()
738 DMask = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); in setMI()
887 unsigned MaxMask = std::max(CI.DMask, Paired.DMask); in dmasksCanBeCombined()
888 unsigned MinMask = std::min(CI.DMask, Paired.DMask); in dmasksCanBeCombined()
1325 unsigned MergedDMask = CI.DMask | Paired.DMask; in mergeImagePair()
1787 assert(((unsigned)llvm::popcount(CI.DMask | Paired.DMask) == Width) && in getNewOpcode()
1797 ((unsigned)llvm::popcount(CI.DMask | Paired.DMask) == in getSubRegIdxs()
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| H A D | AMDGPUInstCombineIntrinsic.cpp | 1139 ConstantInt *DMask = cast<ConstantInt>(Args[DMaskIdx]); in simplifyAMDGCNMemoryIntrinsicDemanded() local
1140 unsigned DMaskVal = DMask->getZExtValue() & 0xf; in simplifyAMDGCNMemoryIntrinsicDemanded()
1157 Args[DMaskIdx] = ConstantInt::get(DMask->getType(), NewDMaskVal); in simplifyAMDGCNMemoryIntrinsicDemanded()
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| H A D | AMDGPULegalizerInfo.cpp | 4890 unsigned DMask = 0; in legalizeImageIntrinsic() local
4905 DMask = MI.getOperand(ArgOffset + Intr->DMaskIndex).getImm(); in legalizeImageIntrinsic()
4908 } else if (DMask != 0) { in legalizeImageIntrinsic()
4909 DMaskLanes = llvm::popcount(DMask); in legalizeImageIntrinsic()
4932 if (IsTFE && DMask == 0) { in legalizeImageIntrinsic()
4933 DMask = 0x1; in legalizeImageIntrinsic()
4935 MI.getOperand(ArgOffset + Intr->DMaskIndex).setImm(DMask); in legalizeImageIntrinsic()
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| H A D | AMDGPUInstructionSelector.cpp | 1786 unsigned DMask = 0; in selectImageIntrinsic() local
1802 DMask = Is64Bit ? 0xf : 0x3; in selectImageIntrinsic()
1805 DMask = Is64Bit ? 0x3 : 0x1; in selectImageIntrinsic()
1809 DMask = MI.getOperand(ArgOffset + Intr->DMaskIndex).getImm(); in selectImageIntrinsic()
1810 DMaskLanes = BaseOpcode->Gather4 ? 4 : llvm::popcount(DMask); in selectImageIntrinsic()
1940 MIB.addImm(DMask); // dmask in selectImageIntrinsic()
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| H A D | SIISelLowering.cpp | 1014 unsigned DMask in getTgtMemIntrinsic() local
1016 MaxNumLanes = DMask == 0 ? 1 : llvm::popcount(DMask); in getTgtMemIntrinsic()
1030 unsigned DMask = cast<ConstantInt>(CI.getArgOperand(1))->getZExtValue(); in getTgtMemIntrinsic() local
1031 unsigned DMaskLanes = DMask == 0 ? 1 : llvm::popcount(DMask); in getTgtMemIntrinsic()
6409 unsigned DMask; in lowerImage() local
6424 DMask = Is64Bit ? 0xf : 0x3; in lowerImage()
6427 DMask = Is64Bit ? 0x3 : 0x1; in lowerImage()
6433 DMask = DMaskConst->getZExtValue(); in lowerImage()
6434 DMaskLanes = BaseOpcode->Gather4 ? 4 : llvm::popcount(DMask); in lowerImage()
6608 DMask = 0x1; in lowerImage()
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| H A D | SIInstrInfo.cpp | 4344 const MachineOperand *DMask = getNamedOperand(MI, AMDGPU::OpName::dmask); in verifyInstruction() local
4345 if (DMask) { in verifyInstruction()
4346 uint64_t DMaskImm = DMask->getImm(); in verifyInstruction()
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| H A D | SIInstrInfo.td | 1267 def DMask : NamedIntOperand<i16, "dmask">;
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 3623 unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf; in validateMIMGDataSize() local
3624 if (DMask == 0) in validateMIMGDataSize()
3625 DMask = 1; in validateMIMGDataSize()
3629 (Desc.TSFlags & SIInstrFlags::Gather4) ? 4 : llvm::popcount(DMask); in validateMIMGDataSize()
3709 unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf; in validateMIMGAtomicDMask() local
3715 return DMask == 0x1 || DMask == 0x3 || DMask == 0xf; in validateMIMGAtomicDMask()
3727 unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf; in validateMIMGGatherDMask() local
3734 return DMask == 0x1 || DMask == 0x2 || DMask == 0x4 || DMask == 0x8; in validateMIMGGatherDMask()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 937 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; in convertMIMGInst() local
938 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); in convertMIMGInst()
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| /openbsd-src/gnu/llvm/llvm/include/llvm/IR/ |
| H A D | IntrinsicsAMDGPU.td | 827 // Marker class for intrinsics with a DMask that determines the returned
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 41561 int DMask[] = {0, 1, 2, 3}; in combineTargetShuffle() local
41563 DMask[DOffset + 0] = DOffset + 1; in combineTargetShuffle()
41564 DMask[DOffset + 1] = DOffset + 0; in combineTargetShuffle()
41568 getV4X86ShuffleImm8ForMask(DMask, DL, DAG)); in combineTargetShuffle()
41583 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D); in combineTargetShuffle() local
41594 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2; in combineTargetShuffle()
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