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Searched refs:CreateReg (Results 1 – 25 of 71) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstrBuilder.h69 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false, in getFullAddress()
77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, in getFullAddress()
85 MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false, in getFullAddress()
H A DX86KCFI.cpp103 Check->addOperand(MachineOperand::CreateReg(Target.getReg(), false)); in emitCheck()
113 Check->addOperand(MachineOperand::CreateReg(X86::R11, false)); in emitCheck()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIFixVGPRCopies.cpp59 MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); in runOnMachineFunction()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp212 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); in runOnMachineFunction()
219 MI.addOperand(MachineOperand::CreateReg( in runOnMachineFunction()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp639 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in addStackMapLiveVars()
687 Ops.push_back(MachineOperand::CreateReg( in selectStackmap()
798 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*isDef=*/true)); in selectPatchpoint()
847 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in selectPatchpoint()
853 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in selectPatchpoint()
866 Ops.push_back(MachineOperand::CreateReg( in selectPatchpoint()
872 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/true, in selectPatchpoint()
900 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)), in selectXRayCustomEvent()
902 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)), in selectXRayCustomEvent()
919 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)), in selectXRayTypedEvent()
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H A DFunctionLoweringInfo.cpp367 Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) { in CreateReg() function in FunctionLoweringInfo
389 Register R = CreateReg(RegisterVT, isDivergent); in CreateRegs()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCTOCRegDeps.cpp121 MI.addOperand(MachineOperand::CreateReg(TOCReg, in processBlock()
H A DPPCPreEmitPeephole.cpp340 MachineOperand::CreateReg(Pair->UseReg, true, true); in addLinkerOpt()
342 MachineOperand::CreateReg(Pair->UseReg, false, true); in addLinkerOpt()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp218 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
248 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
H A DARMBaseInstrInfo.h545 MachineOperand::CreateReg(PredReg, false)}};
551 return MachineOperand::CreateReg(CCReg, false);
558 return MachineOperand::CreateReg(ARM::CPSR,
H A DThumb2InstrInfo.cpp585 MI.addOperand(MachineOperand::CreateReg(0, false)); in rewriteT2FrameIndex()
617 MI.addOperand(MachineOperand::CreateReg(0, false)); in rewriteT2FrameIndex()
H A DARMSLSHardening.cpp352 BL->addOperand(MachineOperand::CreateReg(Reg, false /*isDef*/, true /*isImp*/, in ConvertIndirectCallToIndirectJump()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DLiveVariables.cpp244 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
256 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
267 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
380 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegKill()
397 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, in HandlePhysRegKill()
H A DMachineOutliner.cpp846 MachineOperand::CreateReg(I, true, /* isDef = true */ in outline()
852 MachineOperand::CreateReg(I, false, /* isDef = false */ in outline()
H A DMachineInstr.cpp88 addOperand(MF, MachineOperand::CreateReg(ImpDef, true, true)); in addImplicitDefUseOperands()
90 addOperand(MF, MachineOperand::CreateReg(ImpUse, false, true)); in addImplicitDefUseOperands()
1947 addOperand(MachineOperand::CreateReg(IncomingReg, in addRegisterKilled()
2013 addOperand(MachineOperand::CreateReg(Reg, in addRegisterDead()
2050 addOperand(MachineOperand::CreateReg(Reg, in addRegisterDefined()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp471 Ldst.addOperand(MachineOperand::CreateReg(NewBase, true)); in changeToAddrMode()
474 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false)); in changeToAddrMode()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DFunctionLoweringInfo.h202 Register CreateReg(MVT VT, bool isDivergent = false);
/openbsd-src/gnu/llvm/llvm/lib/Target/MSP430/AsmParser/
H A DMSP430AsmParser.cpp201 static std::unique_ptr<MSP430Operand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anone9cbbf050111::MSP430Operand
462 Operands.push_back(MSP430Operand::CreateReg(RegNo, StartLoc, EndLoc)); in ParseOperand()
/openbsd-src/gnu/llvm/llvm/lib/Target/AVR/AsmParser/
H A DAVRAsmParser.cpp214 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anond633fba90111::AVROperand
416 Operands.push_back(AVROperand::CreateReg(RegNo, T.getLoc(), T.getEndLoc())); in tryParseRegisterOperand()
/openbsd-src/gnu/llvm/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp600 static std::unique_ptr<VEOperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anon0d4fa8ad0211::VEOperand
1473 Operands.push_back(VEOperand::CreateReg(RegNo1, S1, E1)); in parseOperand()
1474 Operands.push_back(VEOperand::CreateReg(RegNo2, S2, E2)); in parseOperand()
1532 Op = VEOperand::CreateReg(RegNo, S, E); in parseVEAsmOperand()
/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp85 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, in imposeStackOrdering()
91 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, in imposeStackOrdering()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DCSEInfo.cpp371 addNodeIDMachineOperand(MachineOperand::CreateReg(Reg, false)); in addNodeIDRegType()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64SLSHardening.cpp373 BL->addOperand(MachineOperand::CreateReg(Reg, false /*isDef*/, true /*isImp*/, in ConvertBLRToBL()
/openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp453 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, in CreateReg() function in __anon4ad277090211::SparcOperand
1061 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E)); in parseOperand()
1121 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E); in parseSparcAsmOperand()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp2169 CreateReg(unsigned RegNum, RegKind Kind, SMLoc S, SMLoc E, MCContext &Ctx, in CreateReg() function in __anonb6c3df290111::AArch64Operand
2197 auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount, in CreateVectorReg()
3141 Operands.push_back(AArch64Operand::CreateReg( in tryParseSyspXzrPair()
4598 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPR64sp0Operand()
4617 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPR64sp0Operand()
4633 Operands.push_back(AArch64Operand::CreateReg( in tryParseZTOperand()
4670 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPROperand()
4685 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPROperand()
6224 Operands[2] = AArch64Operand::CreateReg( in MatchAndEmitInstruction()
6387 Operands[2] = AArch64Operand::CreateReg(Reg, RegKind::Scalar, in MatchAndEmitInstruction()
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