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/openbsd-src/gnu/llvm/compiler-rt/lib/scudo/standalone/
H A Dlinux.cpp139 cpu_set_t CPUs; in getNumberOfCPUs() local
142 if (sched_getaffinity(0, sizeof(cpu_set_t), &CPUs) != 0) in getNumberOfCPUs()
144 return static_cast<u32>(CPU_COUNT(&CPUs)); in getNumberOfCPUs()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86SchedPredicates.td65 // on recent Intel CPUs.
77 // on recent Intel CPUs.
H A DX86.td100 // is used to enforce that only 64-bit capable CPUs are used in 64-bit mode.
433 // FIXME: This should not apply to CPUs that do not have SSE.
612 … "Indicates if gather is reasonably fast (this is true for Skylake client and all AVX-512 CPUs)">;
1477 // Atom CPUs.
1568 // AMD CPUs.
/openbsd-src/gnu/llvm/llvm/include/llvm/Target/
H A DTargetPfmCounters.td49 // Declares the default binding for unbound CPUs for the target.
/openbsd-src/gnu/usr.bin/binutils-2.17/gas/doc/
H A Dasconfig.texi27 @c CPUs of interest
H A Dall.texi27 @c CPUs of interest
/openbsd-src/gnu/usr.bin/binutils/gas/doc/
H A Dall.texi27 @c CPUs of interest
/openbsd-src/gnu/llvm/llvm/docs/tutorial/MyFirstLanguageFrontend/
H A DLangImpl08.rst87 To see which features and CPUs that LLVM knows about, we can use
93 Available CPUs for this target:
/openbsd-src/gnu/gcc/gcc/config/sh/
H A Dlinux-atomic.asm27 !! Linux specific atomic routines for the Renesas / SuperH SH CPUs.
/openbsd-src/gnu/llvm/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_linux_libcdep.cpp841 cpu_set_t CPUs; in GetNumberOfCPUs()
842 CHECK_EQ(sched_getaffinity(0, sizeof(cpu_set_t), &CPUs), 0); in GetNumberOfCPUs()
843 return CPU_COUNT(&CPUs); in GetNumberOfCPUs()
/openbsd-src/gnu/llvm/llvm/docs/
H A DYamlIO.rst292 For instance, suppose you had an enumeration of CPUs and a struct with it as
297 enum CPUs {
304 CPUs cpu;
309 ScalarEnumerationTraits specialization on CPUs, which can then be used
319 struct ScalarEnumerationTraits<CPUs> {
320 static void enumeration(IO &io, CPUs &value) {
737 CPUs cpu;
H A DHowToBuildOnARM.rst18 ARM encompasses a wide variety of CPUs; this advice is primarily based
H A DAtomics.rst424 primitives. However, on many older CPUs (e.g. ARMv5, SparcV8, Intel 80386) there
565 Some CPUs support multiple instruction sets which can be switched back and forth
575 function which on older CPUs contains a "magically-restartable" atomic sequence
578 be provided on any architecture, if all CPUs which are missing atomic
H A DCompileCudaWithLLVM.rst101 GPU hardware allows for more control over numerical operations than most CPUs,
502 Modern CPUs and GPUs are architecturally quite different, so code that's fast
533 function inlining need to be more aggressive for GPUs than for CPUs because
/openbsd-src/distrib/notes/octeon/
H A Dinstall83 On multi-core systems, the numcores parameter enables the secondary CPUs.
/openbsd-src/gnu/llvm/llvm/lib/Support/Unix/
H A DThreading.inc386 // system has more than 1024 CPUs). Allocate a mask large enough for
387 // twice as many CPUs.
/openbsd-src/share/snmp/
H A DVM-MIB.txt601 "The number of virtual CPUs currently assigned to the
610 "The minimum number of virtual CPUs that are assigned to
613 the minimum number of virtual CPUs."
621 "The maximum number of virtual CPUs that are assigned to
686 of virtual CPUs is larger than 1, vmCpuTime may exceed
702 "The table of virtual CPUs provided by the hypervisor."
/openbsd-src/gnu/llvm/llvm/docs/CommandGuide/
H A Dlli.rst85 the current architecture. For a list of available CPUs, use:
H A Dllc.rst73 the current architecture. For a list of available CPUs, use:
/openbsd-src/gnu/llvm/lldb/docs/use/
H A Dintel_pt.rst7 Intel PT is a technology available in modern Intel CPUs that allows efficient
/openbsd-src/gnu/gcc/gcc/config/i386/
H A Dppro.md22 ;; and Xeon lines of CPUs. The DFA scheduler description in this file is
39 ;; So, the P6 CPUs have out-of-order cores, but the instruction decoder and
51 ;; Since the P6 CPUs execute instructions out-of-order, the most important
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64.td192 /// CPUs.
1420 // iPhone and iPad CPUs
1442 // Mac CPUs
1448 // watch CPUs.
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPC.td417 // they will be part of any future CPUs. One example is the narrower
420 // enough info to create custom scheduling strategies for future CPUs.
/openbsd-src/gnu/llvm/lld/docs/
H A Dindex.rst25 - It supports various CPUs/ABIs including AArch64, AMDGPU, ARM, Hexagon, MIPS
/openbsd-src/gnu/llvm/clang/docs/
H A DSafeStack.rst112 CPUs).

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