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Searched refs:BuildMI (Results 1 – 25 of 338) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsReturnProtectorLowering.cpp58 BuildMI(MBB, MI, MBBDL, TII->get(Mips::LUi64), TempReg1) in insertReturnProtectorPrologue()
60 BuildMI(MBB, MI, MBBDL, TII->get(Mips::LUi64), TempReg2) in insertReturnProtectorPrologue()
62 BuildMI(MBB, MI, MBBDL, TII->get(Mips::DADDu), TempReg1) in insertReturnProtectorPrologue()
65 BuildMI(MBB, MI, MBBDL, TII->get(Mips::DADDiu), TempReg2) in insertReturnProtectorPrologue()
68 BuildMI(MBB, MI, MBBDL, TII->get(Mips::DADDu), TempReg1) in insertReturnProtectorPrologue()
71 BuildMI(MBB, MI, MBBDL, TII->get(Mips::LD), REG) in insertReturnProtectorPrologue()
74 BuildMI(MBB, MI, MBBDL, TII->get(Mips::LD), REG) in insertReturnProtectorPrologue()
80 BuildMI(MBB, MI, MBBDL, TII->get(Mips::LUi64), TempReg1) in insertReturnProtectorPrologue()
82 BuildMI(MBB, MI, MBBDL, TII->get(Mips::LUi64), TempReg2) in insertReturnProtectorPrologue()
84 BuildMI(MBB, MI, MBBDL, TII->get(Mips::DADDiu), TempReg1) in insertReturnProtectorPrologue()
[all …]
H A DMipsExpandPseudo.cpp145 BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0); in expandAtomicCmpSwapSubword()
146 BuildMI(loop1MBB, DL, TII->get(Mips::AND), Scratch2) in expandAtomicCmpSwapSubword()
149 BuildMI(loop1MBB, DL, TII->get(BNE)) in expandAtomicCmpSwapSubword()
157 BuildMI(loop2MBB, DL, TII->get(Mips::AND), Scratch) in expandAtomicCmpSwapSubword()
160 BuildMI(loop2MBB, DL, TII->get(Mips::OR), Scratch) in expandAtomicCmpSwapSubword()
163 BuildMI(loop2MBB, DL, TII->get(SC), Scratch) in expandAtomicCmpSwapSubword()
167 BuildMI(loop2MBB, DL, TII->get(BEQ)) in expandAtomicCmpSwapSubword()
175 BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest) in expandAtomicCmpSwapSubword()
179 BuildMI(sinkMBB, DL, TII->get(SEOp), Dest).addReg(Dest); in expandAtomicCmpSwapSubword()
183 BuildMI(sinkMBB, DL, TII->get(Mips::SLL), Dest) in expandAtomicCmpSwapSubword()
[all …]
H A DMipsBranchExpansion.cpp345 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc); in replaceBranch()
401 BuildMI(*MBB, Pos, DL, TII->get(JumpOp)).addReg(ATReg); in buildProperJumpMI()
470 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
473 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)) in expandToLongBranch()
494 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) in expandToLongBranch()
499 BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB); in expandToLongBranch()
501 BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT) in expandToLongBranch()
516 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT) in expandToLongBranch()
519 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA) in expandToLongBranch()
531 BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
[all …]
H A DMipsInstructionSelector.cpp261 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) in buildUnalignedStore()
275 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) in buildUnalignedLoad()
301 MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL)) in select()
325 PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu)) in select()
332 PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI)) in select()
342 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
354 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
361 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::BNE)) in select()
374 MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL)) in select()
382 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
[all …]
H A DMipsSEFrameLowering.cpp178 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst) in expandLoadCCond()
192 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) in expandStoreCCond()
216 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill); in expandLoadACC()
218 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); in expandLoadACC()
238 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); in expandStoreACC()
240 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandStoreACC()
272 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); in expandCopyACC()
273 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo) in expandCopyACC()
275 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandCopyACC()
276 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi) in expandCopyACC()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchExpandAtomicPseudoInsts.cpp167 BuildMI(LoopMBB, DL, TII->get(LoongArch::DBAR)).addImm(0); in doAtomicBinOpExpansion()
168 BuildMI(LoopMBB, DL, in doAtomicBinOpExpansion()
176 BuildMI(LoopMBB, DL, TII->get(LoongArch::OR), ScratchReg) in doAtomicBinOpExpansion()
181 BuildMI(LoopMBB, DL, TII->get(LoongArch::AND), ScratchReg) in doAtomicBinOpExpansion()
184 BuildMI(LoopMBB, DL, TII->get(LoongArch::NOR), ScratchReg) in doAtomicBinOpExpansion()
189 BuildMI(LoopMBB, DL, TII->get(LoongArch::ADD_W), ScratchReg) in doAtomicBinOpExpansion()
194 BuildMI(LoopMBB, DL, TII->get(LoongArch::SUB_W), ScratchReg) in doAtomicBinOpExpansion()
199 BuildMI(LoopMBB, DL, TII->get(LoongArch::AND), ScratchReg) in doAtomicBinOpExpansion()
204 BuildMI(LoopMBB, DL, TII->get(LoongArch::OR), ScratchReg) in doAtomicBinOpExpansion()
209 BuildMI(LoopMBB, DL, TII->get(LoongArch::XOR), ScratchReg) in doAtomicBinOpExpansion()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCReturnProtectorLowering.cpp65 BuildMI(MBB, MI, MBBDL, TII->get(MFLR), LRReg); in insertReturnProtectorPrologue()
67 BuildMI(MBB, MI, MBBDL, TII->get(PPC::ADDIStocHA8), REG) in insertReturnProtectorPrologue()
70 BuildMI(MBB, MI, MBBDL, TII->get(PPC::LD), REG) in insertReturnProtectorPrologue()
74 BuildMI(MBB, MI, MBBDL, TII->get(XOR), REG) in insertReturnProtectorPrologue()
82 BuildMI(MBB, MI, MBBDL, TII->get(PPC::RETGUARD_LOAD_PC), REG) in insertReturnProtectorPrologue()
86 BuildMI(MBB, MI, MBBDL, TII->get(PPC::RETGUARD_LOAD_GOT), REG) in insertReturnProtectorPrologue()
89 BuildMI(MBB, MI, MBBDL, TII->get(PPC::LWZtoc), REG) in insertReturnProtectorPrologue()
93 BuildMI(MBB, MI, MBBDL, TII->get(PPC::LWZ), REG) in insertReturnProtectorPrologue()
97 BuildMI(MBB, MI, MBBDL, TII->get(XOR), REG) in insertReturnProtectorPrologue()
103 BuildMI(MBB, MI, MBBDL, TII->get(MFLR), LRReg); in insertReturnProtectorPrologue()
[all …]
H A DPPCExpandAtomicPseudoInsts.cpp59 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
60 BuildMI(MBB, MBBI, DL, XOR, Dest1).addReg(Dest0).addReg(Dest1); in PairedCopy()
61 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
64 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1); in PairedCopy()
65 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
67 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
68 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1); in PairedCopy()
162 BuildMI(CurrentMBB, DL, LL, Old).addReg(RA).addReg(RB); in expandAtomicRMW128()
170 BuildMI(CurrentMBB, DL, TII->get(PPC::ADDC8), ScratchLo) in expandAtomicRMW128()
173 BuildMI(CurrentMBB, DL, TII->get(PPC::ADDE8), ScratchHi) in expandAtomicRMW128()
[all …]
H A DPPCFrameLowering.cpp796 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFOCRF8), TempReg); in emitPrologue()
800 BuildMI(MBB, MBBI, dl, MoveFromCondRegInst, TempReg); in emitPrologue()
810 BuildMI(MBB, MBBI, dl, StoreWordInst) in emitPrologue()
817 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg); in emitPrologue()
824 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
829 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
834 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
845 BuildMI(MBB, StackUpdateLoc, dl, StoreInst) in emitPrologue()
863 BuildMI(MBB, StackUpdateLoc, dl, HashST) in emitPrologue()
876 BuildMI(MBB, MBBI, dl, StoreWordInst) in emitPrologue()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp167 MachineInstr &MI = *BuildMI(&MBB, DL, get(CSKY::BR32)).addMBB(TBB); in insertBranch()
175 MachineInstr &CondMI = *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).addMBB(TBB); in insertBranch()
184 MachineInstr &MI = *BuildMI(&MBB, DL, get(CSKY::BR32)).addMBB(FBB); in insertBranch()
238 BuildMI(MBB, MBBI, DL, get(CSKY::MOVI32), DstReg) in movImm()
242 BuildMI(MBB, MBBI, DL, get(CSKY::MOVIH32), DstReg) in movImm()
246 BuildMI(MBB, MBBI, DL, get(CSKY::MOVIH32), DstReg) in movImm()
249 BuildMI(MBB, MBBI, DL, get(CSKY::ORI32), DstReg) in movImm()
258 BuildMI(MBB, MBBI, DL, get(CSKY::MOVI16), DstReg) in movImm()
262 BuildMI(MBB, MBBI, DL, get(CSKY::MOVI16), DstReg) in movImm()
265 BuildMI(MBB, MBBI, DL, get(CSKY::LSLI16), DstReg) in movImm()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/VE/
H A DVEFrameLowering.cpp152 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
157 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
164 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
169 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
176 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
200 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX17) in emitEpilogueInsns()
205 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX16) in emitEpilogueInsns()
209 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX15) in emitEpilogueInsns()
215 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX10) in emitEpilogueInsns()
219 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX9) in emitEpilogueInsns()
[all …]
H A DVEInstrInfo.cpp238 BuildMI(&MBB, DL, get(VE::BRCFLa_t)) in insertBranch()
270 BuildMI(&MBB, DL, get(opc[0])) in insertBranch()
276 BuildMI(&MBB, DL, get(opc[1])) in insertBranch()
286 BuildMI(&MBB, DL, get(VE::BRCFLa_t)) in insertBranch()
342 BuildMI(MBB, I, DL, MCID, SubDest).addReg(SubSrc).addImm(0); in copyPhysSubRegs()
347 BuildMI(MBB, I, DL, MCID, SubDest).addReg(VE::VM0).addReg(SubSrc); in copyPhysSubRegs()
365 BuildMI(MBB, I, DL, get(VE::ORri), DestReg) in copyPhysReg()
378 BuildMI(MBB, I, DL, get(VE::LEAzii), TmpReg) in copyPhysReg()
382 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(VE::VORmvl), DestReg) in copyPhysReg()
388 BuildMI(MBB, I, DL, get(VE::ANDMmm), DestReg) in copyPhysReg()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp188 BuildMI(MBB, I, DbgLoc, TII.get(PPC::MTVSRD), MoveReg).addReg(SrcReg); in selectIntToFP()
196 BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), DstReg).addReg(MoveReg); in selectIntToFP()
213 BuildMI(MBB, I, DbgLoc, TII.get(TargetOpcode::COPY), CopyReg).addReg(SrcReg); in selectFPToInt()
223 BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), ConvReg).addReg(CopyReg); in selectFPToInt()
226 BuildMI(MBB, I, DbgLoc, TII.get(PPC::MFVSRD), DstReg).addReg(ConvReg); in selectFPToInt()
245 BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::IMPLICIT_DEF), in selectZExt()
250 BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::INSERT_SUBREG), in selectZExt()
257 BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), DstReg) in selectZExt()
296 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), Reg) in selectI64ImmDirect()
302 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LIS8), Reg) in selectI64ImmDirect()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp233 BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg) in doAtomicBinOpExpansion()
239 BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg) in doAtomicBinOpExpansion()
242 BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg) in doAtomicBinOpExpansion()
247 BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg) in doAtomicBinOpExpansion()
250 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in doAtomicBinOpExpansion()
267 BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg) in insertMaskedMerge()
270 BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg) in insertMaskedMerge()
273 BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg) in insertMaskedMerge()
299 BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg) in doMaskedAtomicBinOpExpansion()
305 BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg) in doMaskedAtomicBinOpExpansion()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp36 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg) in copyPhysReg()
39 BuildMI(MBB, I, DL, get(BPF::MOV_rr_32), DestReg) in copyPhysReg()
78 BuildMI(*BB, MI, dl, get(LdOpc)) in expandMEMCPY()
81 BuildMI(*BB, MI, dl, get(StOpc)) in expandMEMCPY()
92 BuildMI(*BB, MI, dl, get(BPF::LDW)) in expandMEMCPY()
94 BuildMI(*BB, MI, dl, get(BPF::STW)) in expandMEMCPY()
99 BuildMI(*BB, MI, dl, get(BPF::LDH)) in expandMEMCPY()
101 BuildMI(*BB, MI, dl, get(BPF::STH)) in expandMEMCPY()
106 BuildMI(*BB, MI, dl, get(BPF::LDB)) in expandMEMCPY()
108 BuildMI(*BB, MI, dl, get(BPF::STB)) in expandMEMCPY()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AVR/
H A DAVRFrameLowering.cpp64 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs)) in emitPrologue()
72 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
76 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), STI.getTmpRegister()) in emitPrologue()
79 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
83 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
86 BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr)) in emitPrologue()
110 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPREAD), AVR::R29R28) in emitPrologue()
127 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28) in emitPrologue()
135 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP) in emitPrologue()
154 BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), STI.getZeroRegister()); in restoreStatusRegister()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp151 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) in expandMOVImm()
161 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) in expandMOVImm()
172 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) in expandMOVImm()
219 BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::MOVZWi), StatusReg) in expandCMP_SWAP()
221 BuildMI(LoadCmpBB, MIMD, TII->get(LdarOp), Dest.getReg()) in expandCMP_SWAP()
223 BuildMI(LoadCmpBB, MIMD, TII->get(CmpOp), ZeroReg) in expandCMP_SWAP()
227 BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::Bcc)) in expandCMP_SWAP()
237 BuildMI(StoreBB, MIMD, TII->get(StlrOp), StatusReg) in expandCMP_SWAP()
240 BuildMI(StoreBB, MIMD, TII->get(AArch64::CBNZW)) in expandCMP_SWAP()
325 BuildMI(LoadCmpBB, MIMD, TII->get(LdxpOp)) in expandCMP_SWAP_128()
[all …]
H A DAArch64ReturnProtectorLowering.cpp42 BuildMI(MBB, MI, MBBDL, TII->get(AArch64::ADRP), REG) in insertReturnProtectorPrologue()
44 BuildMI(MBB, MI, MBBDL, TII->get(AArch64::LDRXui), REG) in insertReturnProtectorPrologue()
47 BuildMI(MBB, MI, MBBDL, TII->get(AArch64::EORXrr), REG) in insertReturnProtectorPrologue()
64 BuildMI(MBB, MI, MBBDL, TII->get(AArch64::EORXrr), REG) in insertReturnProtectorEpilogue()
67 BuildMI(MBB, MI, MBBDL, TII->get(AArch64::ADRP), AArch64::X9) in insertReturnProtectorEpilogue()
69 BuildMI(MBB, MI, MBBDL, TII->get(AArch64::LDRXui), AArch64::X9) in insertReturnProtectorEpilogue()
72 BuildMI(MBB, MI, MBBDL, TII->get(AArch64::SUBSXrr), REG) in insertReturnProtectorEpilogue()
75 BuildMI(MBB, MI, MBBDL, TII->get(AArch64::RETGUARD_JMP_TRAP)).addReg(REG); in insertReturnProtectorEpilogue()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp243 BuildMI(MBB, MBBI, DL, TII.get(X86::STACKALLOC_W_PROBING)).addImm(Offset); in emitSPUpdate()
259 BuildMI(MBB, MBBI, DL, TII.get(getMOVriOpcode(Is64Bit, Offset)), Reg) in emitSPUpdate()
262 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr) in emitSPUpdate()
276 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r)) in emitSPUpdate()
285 BuildMI(MBB, MBBI, DL, TII.get(getMOVriOpcode(Is64Bit, Offset)), Rax) in emitSPUpdate()
288 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(X86::ADD64rr), Rax) in emitSPUpdate()
294 BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax), in emitSPUpdate()
297 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr), in emitSPUpdate()
315 BuildMI(MBB, MBBI, DL, TII.get(Opc)) in emitSPUpdate()
361 MI = addRegOffset(BuildMI(MBB, MBBI, DL, in BuildStackAdjustment()
[all …]
H A DX86ExpandPseudo.cpp107 BuildMI(*MBB, MBBI, DL, TII->get(X86::LEA64r), X86::R11) in INITIALIZE_PASS()
114 BuildMI(*MBB, MBBI, DL, TII->get(X86::CMP64rr)) in INITIALIZE_PASS()
128 BuildMI(*MBB, MBBI, DL, TII->get(X86::JCC_1)).addMBB(ThenMBB).addImm(CC); in INITIALIZE_PASS()
143 BuildMI(*MBB, MBBI, DL, TII->get(X86::TAILJMPd64)) in INITIALIZE_PASS()
185 BuildMI(P.first, DL, TII->get(X86::TAILJMPd64)) in INITIALIZE_PASS()
210 OriginalCall = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)).getInstr(); in expandCALL_RVMARKER()
230 auto *Marker = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(X86::MOV64rr)) in expandCALL_RVMARKER()
241 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(X86::CALL64pcrel32)) in expandCALL_RVMARKER()
328 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op)); in ExpandMI()
345 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op)); in ExpandMI()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMFrameLowering.cpp315 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
324 BuildMI(MF, DL, TII.get(ARM::tMOVi8)).setMIFlags(MBBI->getFlags()); in insertSEH()
333 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)).addImm(Wide).setMIFlags(Flags); in insertSEH()
338 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
351 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
355 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
365 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs)) in insertSEH()
379 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs)) in insertSEH()
422 BuildMI(MF, DL, TII.get(NewOpc)).setMIFlags(MBBI->getFlags()); in insertSEH()
431 MIB = BuildMI(MF, DL, TII.get(SEHOpc)) in insertSEH()
[all …]
H A DARMExpandPseudoInsts.cpp577 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD()
698 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVST()
775 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandLaneOp()
860 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); in ExpandVTBL()
899 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMQQPRLoadStore()
996 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); in ExpandMOV32BitImm()
997 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) in ExpandMOV32BitImm()
1003 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi), DstReg); in ExpandMOV32BitImm()
1004 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri)) in ExpandMOV32BitImm()
1039 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg); in ExpandMOV32BitImm()
[all …]
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h357 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, in BuildMI() function
365 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, in BuildMI() function
375 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
393 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
405 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I, in BuildMI() function
411 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), MIMD, MCID, in BuildMI()
413 return BuildMI(BB, MachineBasicBlock::iterator(I), MIMD, MCID, DestReg); in BuildMI()
416 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I, in BuildMI() function
419 return BuildMI(BB, *I, MIMD, MCID, DestReg); in BuildMI()
425 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp72 BuildMI(MBB, MBBI, dl, TII.get(AdjOp), StackPtr) in generateStackAdjustment()
142 BuildMI(MBB, MBBI, dl, TII->get(Opc), ARC::SP) in emitPrologue()
148 BuildMI(MBB, MBBI, dl, TII->get(ARC::ST_AW_rs9)) in emitPrologue()
159 BuildMI(MBB, MBBI, dl, TII->get(ARC::PUSH_S_BLINK)); in emitPrologue()
160 BuildMI(MBB, MBBI, dl, TII->get(ARC::SUB_rru6)) in emitPrologue()
164 BuildMI(MBB, MBBI, dl, TII->get(ARC::BL)) in emitPrologue()
173 BuildMI(MBB, MBBI, dl, TII->get(ARC::PUSH_S_BLINK)); in emitPrologue()
186 BuildMI(MBB, MBBI, dl, in emitPrologue()
200 BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
208 BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcFrameLowering.cpp52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) in emitSPAdjustment()
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) in emitSPAdjustment()
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1) in emitSPAdjustment()
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
156 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
161 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
169 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
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