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/openbsd-src/gnu/llvm/llvm/tools/llvm-exegesis/lib/
H A DRegisterAliasing.h28 BitVector getAliasedBits(const MCRegisterInfo &RegInfo,
29 const BitVector &SourceBits);
44 const BitVector &ReservedReg,
51 const BitVector &sourceBits() const { return SourceBits; } in sourceBits()
54 const BitVector &aliasedBits() const { return AliasedBits; } in aliasedBits()
68 const BitVector &OriginalBits);
70 BitVector SourceBits;
71 BitVector AliasedBits;
79 const BitVector &ReservedReg);
82 const BitVector &emptyRegisters() const { return EmptyRegisters; } in emptyRegisters()
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H A DMCInstrDescView.h98 const BitVector *getUnique(BitVector &&BV) const;
101 mutable std::vector<std::unique_ptr<BitVector>> Cache;
134 bool hasAliasingRegisters(const BitVector &ForbiddenRegisters) const;
138 const BitVector &ForbiddenRegisters) const;
159 const BitVector &ImplDefRegs; // The set of aliased implicit def registers.
160 const BitVector &ImplUseRegs; // The set of aliased implicit use registers.
161 const BitVector &AllDefRegs; // The set of all aliased def registers.
162 const BitVector &AllUseRegs; // The set of all aliased use registers.
166 SmallVector<Variable, 4> Variables, const BitVector *ImplDefRegs,
167 const BitVector *ImplUseRegs, const BitVector *AllDefRegs,
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H A DParallelSnippetGenerator.cpp147 const LLVMState &State, const BitVector &ForbiddenRegisters, in generateSingleRegisterForInstrAvoidingDefUseOverlap()
148 const BitVector &ImplicitUseAliases, const BitVector &ImplicitDefAliases, in generateSingleRegisterForInstrAvoidingDefUseOverlap()
149 const BitVector &Uses, const BitVector &Defs, const InstructionTemplate &IT, in generateSingleRegisterForInstrAvoidingDefUseOverlap()
168 BitVector PossibleRegisters = Op.getRegisterAliasing().sourceBits(); in generateSingleRegisterForInstrAvoidingDefUseOverlap()
169 const BitVector UseAliases = getAliasedBits(State.getRegInfo(), Uses); in generateSingleRegisterForInstrAvoidingDefUseOverlap()
178 BitVector PossibleRegisters = Op.getRegisterAliasing().sourceBits(); in generateSingleRegisterForInstrAvoidingDefUseOverlap()
183 const BitVector UseAliases = getAliasedBits(State.getRegInfo(), Uses); in generateSingleRegisterForInstrAvoidingDefUseOverlap()
191 const BitVector UseAliases = getAliasedBits(State.getRegInfo(), Uses); in generateSingleRegisterForInstrAvoidingDefUseOverlap()
203 const BitVector DefsAliases = getAliasedBits(State.getRegInfo(), Defs); in generateSingleRegisterForInstrAvoidingDefUseOverlap()
215 const LLVMState &State, const BitVector &ForbiddenRegisters, in generateSingleSnippetForInstrAvoidingDefUseOverlap()
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H A DSnippetGenerator.h39 const BitVector &ForbiddenRegisters);
67 const BitVector &ExtraForbiddenRegs) const;
81 const BitVector &ForbiddenRegisters) const = 0;
94 size_t randomBit(const BitVector &Vector);
97 std::optional<int> getFirstCommonBit(const BitVector &A, const BitVector &B);
107 const BitVector &ForbiddenRegs,
H A DRegisterAliasing.cpp14 BitVector getAliasedBits(const MCRegisterInfo &RegInfo, in getAliasedBits()
15 const BitVector &SourceBits) { in getAliasedBits()
16 BitVector AliasedBits(RegInfo.getNumRegs()); in getAliasedBits()
32 const MCRegisterInfo &RegInfo, const BitVector &ReservedReg, in RegisterAliasingTracker()
49 const MCRegisterInfo &RegInfo, const BitVector &SourceBits) { in FillOriginAndAliasedBits()
61 const MCRegisterInfo &RegInfo, const BitVector &ReservedReg) in RegisterAliasingTrackerCache()
82 std::string debugString(const MCRegisterInfo &RegInfo, const BitVector &Regs) { in debugString()
H A DMCInstrDescView.cpp83 const BitVector *BitVectorCache::getUnique(BitVector &&BV) const { in getUnique()
87 Cache.push_back(std::make_unique<BitVector>()); in getUnique()
96 const BitVector *ImplDefRegs, in Instruction()
97 const BitVector *ImplUseRegs, in Instruction()
98 const BitVector *AllDefRegs, in Instruction()
99 const BitVector *AllUseRegs) in Instruction()
166 BitVector ImplDefRegs = RATC.emptyRegisters(); in create()
167 BitVector ImplUseRegs = RATC.emptyRegisters(); in create()
168 BitVector AllDefRegs = RATC.emptyRegisters(); in create()
169 BitVector AllUseRegs = RATC.emptyRegisters(); in create()
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H A DSnippetGenerator.cpp43 const BitVector &ExtraForbiddenRegs) const { in generateConfigurations()
44 BitVector ForbiddenRegs = State.getRATC().reservedRegisters(); in generateConfigurations()
107 BitVector DefinedRegs = State.getRATC().emptyRegisters(); in computeRegisterInitialValues()
145 const BitVector &ForbiddenRegisters) { in generateSelfAliasingCodeTemplates()
210 size_t randomBit(const BitVector &Vector) { in randomBit()
218 std::optional<int> getFirstCommonBit(const BitVector &A, const BitVector &B) { in getFirstCommonBit()
219 BitVector Intersect = A; in getFirstCommonBit()
239 const BitVector &ForbiddenRegs) { in randomizeMCOperand()
273 const BitVector &ForbiddenRegs, in randomizeUnsetVariables()
/openbsd-src/gnu/llvm/llvm/include/llvm/ADT/
H A DBitVector.h75 class BitVector {
98 reference(BitVector &b, unsigned Idx) { in reference()
124 typedef const_set_bits_iterator_impl<BitVector> const_set_bits_iterator;
138 BitVector() = default;
142 explicit BitVector(unsigned s, bool t = false)
344 BitVector &set() { in set()
350 BitVector &set(unsigned Idx) { in set()
357 BitVector &set(unsigned I, unsigned E) { in set()
385 BitVector &reset() { in reset()
390 BitVector &reset(unsigned Idx) { in reset()
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H A DSmallBitVector.h95 BitVector *getPointer() const { in getPointer()
97 return reinterpret_cast<BitVector *>(X); in getPointer()
106 void switchToLarge(BitVector *BV) { in switchToLarge()
152 switchToLarge(new BitVector(s, t));
160 switchToLarge(new BitVector(*RHS.getPointer())); in SmallBitVector()
340 BitVector *BV = new BitVector(N, t);
353 BitVector *BV = new BitVector(SmallSize); in reserve()
620 switchToLarge(new BitVector(*RHS.getPointer()));
/openbsd-src/gnu/llvm/llvm/lib/Support/
H A DGlobPattern.cpp26 static Expected<BitVector> expand(StringRef S, StringRef Original) { in expand()
27 BitVector BV(256, false); in expand()
66 static Expected<BitVector> scan(StringRef &S, StringRef Original) { in scan()
72 return BitVector(); in scan()
75 return BitVector(256, true); in scan()
87 Expected<BitVector> BV = expand(Chars.substr(1), Original); in scan()
100 BitVector BV(256, false); in scan()
134 Expected<BitVector> BV = scan(S, Original); in create()
153 bool GlobPattern::matchOne(ArrayRef<BitVector> Pats, StringRef S) const { in matchOne()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DRegisterScavenging.h67 BitVector KillRegUnits, DefRegUnits;
68 BitVector TmpRegUnits;
136 BitVector getRegsAvailable(const TargetRegisterClass *RC);
203 void setUsed(const BitVector &RegUnits) { in setUsed()
206 void setUnused(const BitVector &RegUnits) { in setUnused()
215 void addRegUnits(BitVector &BV, MCRegister Reg);
218 void removeRegUnits(BitVector &BV, MCRegister Reg);
225 BitVector &Candidates,
H A DLiveRangeCalc.h63 BitVector Seen;
76 using EntryInfoMap = DenseMap<LiveRange *, std::pair<BitVector, BitVector>>;
130 MachineBasicBlock &MBB, BitVector &DefOnEntry,
131 BitVector &UndefOnEntry);
H A DRDFRegisters.h130 const BitVector &getMaskUnits(RegisterId MaskId) const { in getMaskUnits()
134 const BitVector &getUnitAliases(uint32_t U) const { in getUnitAliases()
150 BitVector Units;
153 BitVector Regs;
179 return DenseMapInfo<BitVector>::isEqual(Units, A.Units);
199 return DenseMapInfo<BitVector>::getHashValue(Units); in hash()
245 BitVector Units;
H A DLiveRegUnits.h32 BitVector Units;
144 void addUnits(const BitVector &RegUnits) { in addUnits()
148 void removeUnits(const BitVector &RegUnits) { in removeUnits()
152 const BitVector &getBitVector() const { in getBitVector()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp100 BitVector Defs, Uses;
103 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {} in DefUseInfo()
127 void getSubRegs(unsigned Reg, BitVector &SRs) const;
128 void expandReg(unsigned Reg, BitVector &Set) const;
129 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
130 BitVector &Uses) const;
146 void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const { in getSubRegs()
151 void HexagonGenMux::expandReg(unsigned Reg, BitVector &Set) const { in expandReg()
158 void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs, in getDefsUses()
159 BitVector &Uses) const { in getDefsUses()
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H A DHexagonFrameLowering.h23 class BitVector; variable
79 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
128 BitVector &DoneT, BitVector &DoneF, BitVector &Path) const;
/openbsd-src/gnu/llvm/llvm/include/llvm/Analysis/
H A DStackLifetime.h46 BitVector Begin;
49 BitVector End;
52 BitVector LiveIn;
55 BitVector LiveOut;
64 BitVector Bits;
113 BitVector InterestingAllocas;
169 static inline raw_ostream &operator<<(raw_ostream &OS, const BitVector &V) {
/openbsd-src/gnu/llvm/llvm/utils/TableGen/GlobalISel/
H A DGIMatchTree.h269 BitVector RemainingInstrNodes;
270 BitVector RemainingEdges;
271 BitVector RemainingPredicates;
274 std::vector<BitVector> UnsatisfiedPredDepsForPred;
279 BitVector TraversableEdges;
280 BitVector TestablePredicates;
334 iterator_range<llvm::BitVector::const_set_bits_iterator>
338 iterator_range<llvm::BitVector::const_set_bits_iterator>
342 iterator_range<llvm::BitVector::const_set_bits_iterator>
453 DenseMap<unsigned, BitVector> Partitions;
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H A DGIMatchTree.cpp86 RemainingInstrNodes(BitVector(MatchDag.getNumInstrNodes(), true)), in GIMatchTreeBuilderLeafInfo()
87 RemainingEdges(BitVector(MatchDag.getNumEdges(), true)), in GIMatchTreeBuilderLeafInfo()
88 RemainingPredicates(BitVector(MatchDag.getNumPredicates(), true)), in GIMatchTreeBuilderLeafInfo()
102 BitVector(PredicateDepIDs.size())); in GIMatchTreeBuilderLeafInfo()
397 BitVector TestedPredicatesForLeaf( in repartition()
469 BitVector Contents(Leaves.size()); in repartition()
493 BitVector Contents(Leaves.size()); in repartition()
510 BitVector Contents(Leaves.size()); in repartition()
522 BitVector Contents(Leaves.size()); in repartition()
537 BitVector PossibleLeaves = getPossibleLeavesForPartition(PartitionIdx); in applyForPartition()
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/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DSpillPlacement.h37 class BitVector; variable
53 BitVector *ActiveNodes;
110 void prepare(BitVector &RegBundles);
H A DStackColoring.cpp418 BitVector Begin;
421 BitVector End;
424 BitVector LiveIn;
427 BitVector LiveOut;
459 BitVector InterestingSlots;
463 BitVector ConservativeSlots;
466 BitVector StoreSlots;
483 using BlockBitVecMap = DenseMap<const MachineBasicBlock *, BitVector>;
489 void dumpBV(const char *tag, const BitVector &BV) const;
564 const BitVector &BV) const { in dumpBV()
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H A DRegUsageInfoCollector.cpp60 static void computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF);
137 BitVector SavedRegs; in runOnMachineFunction()
140 const BitVector &UsedPhysRegsMask = MRI->getUsedPhysRegsMask(); in runOnMachineFunction()
195 computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF) { in computeCalleeSavedRegs()
/openbsd-src/gnu/llvm/llvm/include/llvm/Frontend/OpenMP/
H A DOMPContext.h148 BitVector RequiredTraits = BitVector(unsigned(TraitProperty::Last) + 1);
175 BitVector ActiveTraits = BitVector(unsigned(TraitProperty::Last) + 1);
/openbsd-src/gnu/llvm/llvm/lib/Target/SPIRV/
H A DSPIRVRegisterInfo.cpp24 BitVector SPIRVRegisterInfo::getReservedRegs(const MachineFunction &MF) const { in getReservedRegs()
25 return BitVector(getNumRegs()); in getReservedRegs()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIPostRABundler.cpp52 BitVector &UsedRegUnits) const;
92 BitVector &UsedRegUnits) const { in collectUsedRegUnits()
129 BitVector BundleUsedRegUnits(TRI->getNumRegUnits()); in runOnMachineFunction()
130 BitVector KillUsedRegUnits(TRI->getNumRegUnits()); in runOnMachineFunction()

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