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Searched refs:BaseReg (Results 1 – 25 of 89) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp462 Register BaseReg = LeaI->getOperand(1 + X86::AddrBaseReg).getReg(); in checkRegUsage() local
475 if (TRI->regsOverlap(Reg, BaseReg)) { in checkRegUsage()
514 Register BaseReg = I->getOperand(1 + X86::AddrBaseReg).getReg(); in optLEAALU() local
517 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit); in optLEAALU()
521 if (BaseReg == IndexReg) in optLEAALU()
523 std::swap(BaseReg, IndexReg); in optLEAALU()
526 if (BaseReg == IndexReg) in optLEAALU()
535 .addReg(BaseReg, KilledBase ? RegState::Kill : 0); in optLEAALU()
573 Register BaseReg = Base.getReg(); in optTwoAddrLEA() local
582 if (BaseReg != 0) in optTwoAddrLEA()
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H A DX86InsertPrefetch.cpp83 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
85 return (BaseReg == 0 || in IsMemOpCompatibleWithPrefetch()
86 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) || in IsMemOpCompatibleWithPrefetch()
87 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg)) && in IsMemOpCompatibleWithPrefetch()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARC/
H A DARCRegisterInfo.cpp46 unsigned BaseReg = FrameReg; in replaceFrameIndex() local
51 .addReg(BaseReg) in replaceFrameIndex()
60 BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass); in replaceFrameIndex()
61 if (!BaseReg) { in replaceFrameIndex()
66 BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); in replaceFrameIndex()
67 assert(BaseReg && "Register scavenging failed."); in replaceFrameIndex()
68 LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI) in replaceFrameIndex()
72 RS->setRegUsed(BaseReg); in replaceFrameIndex()
76 .addReg(BaseReg, RegState::Define) in replaceFrameIndex()
94 .addReg(BaseReg, KillState) in replaceFrameIndex()
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H A DARCOptAddrMode.cpp101 MachineOperand &Incr, unsigned BaseReg);
105 void fixPastUses(ArrayRef<MachineInstr *> Uses, unsigned BaseReg,
298 Register BaseReg = Ldst->getOperand(BasePos).getReg(); in canJoinInstructions() local
308 if (Add->getOperand(0).getReg() == StReg || BaseReg == StReg) { in canJoinInstructions()
316 for (MachineInstr &MI : MRI->use_nodbg_instructions(BaseReg)) { in canJoinInstructions()
354 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses() argument
460 Register BaseReg = Ldst.getOperand(BasePos).getReg(); in changeToAddrMode() local
474 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false)); in changeToAddrMode()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DLocalStackSlotAllocation.cpp272 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg() argument
281 return TRI->isFrameOffsetLegal(&MI, BaseReg, Offset); in lookupCandidateBaseReg()
345 Register BaseReg; in insertFrameReferenceRegisters() local
388 if (BaseReg.isValid() && in insertFrameReferenceRegisters()
389 lookupCandidateBaseReg(BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
391 LLVM_DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n"); in insertFrameReferenceRegisters()
407 BaseReg, CandBaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
418 BaseReg = TRI->materializeFrameBaseRegister(Entry, FrameIdx, InstrOffset); in insertFrameReferenceRegisters()
422 << " into " << printReg(BaseReg, TRI) << '\n'); in insertFrameReferenceRegisters()
431 assert(BaseReg && "Unable to allocate virtual base register!"); in insertFrameReferenceRegisters()
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H A DImplicitNullChecks.cpp378 const Register BaseReg = AddrMode.BaseReg, ScaledReg = AddrMode.ScaledReg; in isSuitableMemoryOp() local
383 if (BaseReg != PointerReg && ScaledReg != PointerReg) in isSuitableMemoryOp()
389 if ((BaseReg && in isSuitableMemoryOp()
390 TRI->getRegSizeInBits(BaseReg, MRI) != PointerRegSizeInBits) || in isSuitableMemoryOp()
449 if (CalculateDisplacementFromAddrMode(BaseReg, 1)) in isSuitableMemoryOp()
459 if ((BaseReg && BaseReg != PointerReg && !BaseRegIsConstVal) || in isSuitableMemoryOp()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp125 const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, in emitThumbRegPlusImmInReg() argument
131 (BaseReg != 0 && !isARMLowRegister(BaseReg)); in emitThumbRegPlusImmInReg()
143 assert(BaseReg == ARM::SP && "Unexpected!"); in emitThumbRegPlusImmInReg()
175 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
177 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg()
188 Register BaseReg, int NumBytes, in emitThumbRegPlusImmediate() argument
219 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
231 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
237 } else if (DestReg == BaseReg) { in emitThumbRegPlusImmediate()
240 } else if (isARMLowRegister(BaseReg)) { in emitThumbRegPlusImmediate()
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H A DThumb2InstrInfo.cpp294 Register BaseReg, int NumBytes, in emitT2RegPlusImmediate() argument
298 if (NumBytes == 0 && DestReg != BaseReg) { in emitT2RegPlusImmediate()
300 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
310 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
332 .addReg(BaseReg) in emitT2RegPlusImmediate()
344 .addReg(BaseReg) in emitT2RegPlusImmediate()
357 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate()
360 .addReg(BaseReg) in emitT2RegPlusImmediate()
363 BaseReg = ARM::SP; in emitT2RegPlusImmediate()
367 assert((DestReg != ARM::SP || BaseReg == ARM::SP) && in emitT2RegPlusImmediate()
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H A DARMBaseRegisterInfo.cpp681 Register BaseReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in materializeFrameBaseRegister() local
682 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
684 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister()
690 return BaseReg; in materializeFrameBaseRegister()
693 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex() argument
712 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex()
715 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII, this); in resolveFrameIndex()
722 Register BaseReg, in isFrameOffsetLegal() argument
765 NumBits = (BaseReg == ARM::SP ? 8 : 5); in isFrameOffsetLegal()
H A DThumb2SizeReduction.cpp497 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
498 assert(isARMLowRegister(BaseReg)); in ReduceLoadStore()
504 if (MO.getReg() == BaseReg) { in ReduceLoadStore()
527 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
529 if (MO.getReg() == BaseReg) in ReduceLoadStore()
535 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
536 if (BaseReg != ARM::SP) in ReduceLoadStore()
548 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
549 if (BaseReg == ARM::SP && in ReduceLoadStore()
554 } else if (!isARMLowRegister(BaseReg) || in ReduceLoadStore()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DLoadStoreOpt.cpp85 if (!mi_match(Ptr, MRI, m_GPtrAdd(m_Reg(Info.BaseReg), m_Reg(PtrAddRHS)))) { in getPointerInfo()
86 Info.BaseReg = Ptr; in getPointerInfo()
115 if (!BasePtr0.BaseReg.isValid() || !BasePtr1.BaseReg.isValid()) in aliasIsKnownForLoadStore()
122 if (BasePtr0.BaseReg == BasePtr1.BaseReg) { in aliasIsKnownForLoadStore()
152 auto *Base0Def = getDefIgnoringCopies(BasePtr0.BaseReg, MRI); in aliasIsKnownForLoadStore()
153 auto *Base1Def = getDefIgnoringCopies(BasePtr1.BaseReg, MRI); in aliasIsKnownForLoadStore()
204 Register BaseReg; in instMayAlias() local
208 m_GPtrAdd(m_Reg(BaseReg), m_ICst(Offset)))) { in instMayAlias()
209 BaseReg = LS->getPointerReg(); in instMayAlias()
215 return {LS->isVolatile(), LS->isAtomic(), BaseReg, in instMayAlias()
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/openbsd-src/gnu/llvm/llvm/lib/Target/M68k/
H A DM68kISelDAGToDAG.cpp67 SDValue BaseReg; member
94 return BaseType == Base::FrameIndexBase || BaseReg.getNode() != nullptr; in hasBase()
100 return BaseType == Base::RegBase && BaseReg.getNode() != nullptr; in hasBaseReg()
138 if (auto *RegNode = dyn_cast_or_null<RegisterSDNode>(BaseReg.getNode())) in isPCRelative()
145 BaseReg = Reg; in setBaseReg()
155 if (BaseReg.getNode()) in dump()
156 BaseReg.getNode()->dump(); in dump()
419 AM.BaseReg = N; in matchAddressBase()
494 AM.BaseReg.getNode() == nullptr && doesDispFitFI(AM)) { in matchAddressRecursively()
543 AM.BaseReg = N.getOperand(0); in matchADD()
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/openbsd-src/gnu/llvm/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp427 unsigned BaseReg = 0, IndexReg = 0, TmpReg = 0, Scale = 0; member in __anonbe06ec630111::X86AsmParser::IntelExprStateMachine
459 unsigned getBaseReg() const { return BaseReg; } in getBaseReg()
675 if (!BaseReg) { in onPlus()
676 BaseReg = TmpReg; in onPlus()
734 if (!BaseReg) { in onMinus()
735 BaseReg = TmpReg; in onMinus()
978 if (!BaseReg) { in onRBrac()
979 BaseReg = TmpReg; in onRBrac()
1139 unsigned BaseReg, unsigned IndexReg,
1292 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg, in CheckBaseRegAndIndexRegAndScale() argument
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H A DX86Operand.h65 unsigned BaseReg; member
145 if (Mem.BaseReg) in print()
146 OS << ",BaseReg=" << X86IntelInstPrinter::getRegisterName(Mem.BaseReg); in print()
195 return Mem.BaseReg; in getMemBaseReg()
335 return isMem() && Mem.BaseReg != X86::RIP && Mem.BaseReg != X86::EIP; in isSibMem()
689 Res->Mem.BaseReg = 0;
707 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
715 assert((SegReg || BaseReg || IndexReg || DefaultBaseReg) &&
724 Res->Mem.BaseReg = BaseReg;
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp156 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction() local
157 if (PrevBaseReg == BaseReg) { in runOnMachineFunction()
166 PrevBaseReg = BaseReg; in runOnMachineFunction()
H A DAArch64FalkorHWPFFix.cpp215 Register BaseReg; member
644 Register BaseReg = MI.getOperand(BaseRegIdx).getReg(); in getLoadInfo() local
645 if (BaseReg == AArch64::SP || BaseReg == AArch64::WSP) in getLoadInfo()
650 LI.BaseReg = BaseReg; in getLoadInfo()
661 unsigned Base = TRI->getEncodingValue(LI.BaseReg); in getTag()
755 NewLdI.BaseReg = ScratchReg; in runOnLoop()
772 .addReg(LdI.BaseReg) in runOnLoop()
785 TII->get(AArch64::ORRXrs), LdI.BaseReg) in runOnLoop()
H A DAArch64LoadStoreOptimizer.cpp184 unsigned BaseReg, int Offset);
1224 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(LoadMI).getReg(); in findMatchingStore() local
1253 BaseReg == AArch64InstrInfo::getLdStBaseOp(MI).getReg() && in findMatchingStore()
1269 if (!ModifiedRegUnits.available(BaseReg)) in findMatchingStore()
1530 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(FirstMI).getReg(); in findMatchingInsn() local
1599 if (BaseReg == MIBaseReg) { in findMatchingInsn()
1685 if (!ModifiedRegUnits.available(BaseReg)) in findMatchingInsn()
1752 if (!ModifiedRegUnits.available(BaseReg)) in findMatchingInsn()
1865 unsigned BaseReg, int Offset) { in isMatchingUpdateInsn() argument
1881 if (MI.getOperand(0).getReg() != BaseReg || in isMatchingUpdateInsn()
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H A DAArch64RegisterInfo.h113 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
117 void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
/openbsd-src/gnu/llvm/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp133 unsigned BaseReg; member
175 return Mem.BaseReg; in getMemBaseReg()
618 Op->Mem.BaseReg = 0; in MorphToMemImm()
626 MorphToMemRegReg(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op, in MorphToMemRegReg()
630 Op->Mem.BaseReg = BaseReg; in MorphToMemRegReg()
638 MorphToMemRegImm(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op, in MorphToMemRegImm()
642 Op->Mem.BaseReg = BaseReg; in MorphToMemRegImm()
911 unsigned BaseReg = 0; in parseMemoryOperand() local
968 BaseReg = Op->getReg(); in parseMemoryOperand()
996 if (!BaseReg || Lexer.isNot(AsmToken::RBrac)) { in parseMemoryOperand()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DR600ISelDAGToDAG.cpp27 bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
79 SDValue &BaseReg, in SelectGlobalValueVariableOffset() argument
82 BaseReg = Addr; in SelectGlobalValueVariableOffset()
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.h58 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
64 void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
/openbsd-src/gnu/llvm/llvm/include/llvm/MC/MCParser/
H A DMCTargetAsmParser.h68 StringRef BaseReg; member
74 : NeedBracs(false), Imm(0), BaseReg(StringRef()), IndexReg(StringRef()), in IntelExpr()
79 : NeedBracs(needBracs), Imm(imm), BaseReg(baseReg), IndexReg(indexReg), in IntelExpr()
84 bool hasBaseReg() const { return !BaseReg.empty(); } in hasBaseReg()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.h49 auto BaseReg = MI.getOperand(0).getReg(); in isLDMBaseRegInList() local
52 if (Op.isReg() && Op.getReg() == BaseReg) in isLDMBaseRegInList()
/openbsd-src/gnu/llvm/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp1288 MCRegister BaseReg; in parseMEMOperand() local
1289 if (parseRegister(BaseReg, S, E)) in parseMEMOperand()
1298 ? VEOperand::MorphToMEMrii(BaseReg, IndexValue, std::move(Offset)) in parseMEMOperand()
1299 : VEOperand::MorphToMEMrri(BaseReg, IndexReg, std::move(Offset))); in parseMEMOperand()
1318 MCRegister BaseReg; in parseMEMAsOperand() local
1337 if (parseRegister(BaseReg, S, E)) in parseMEMAsOperand()
1356 Operands.push_back(BaseReg != VE::NoRegister in parseMEMAsOperand()
1357 ? VEOperand::MorphToMEMri(BaseReg, std::move(Offset)) in parseMEMAsOperand()
1362 if (BaseReg != VE::NoRegister) in parseMEMAsOperand()
1370 if (parseRegister(BaseReg, S, E)) in parseMEMAsOperand()
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/openbsd-src/gnu/llvm/llvm/tools/llvm-exegesis/lib/X86/
H A DTarget.cpp277 for (const unsigned BaseReg : PossibleBaseRegs.set_bits()) { in generateLEATemplatesCommon() local
284 setMemOp(IT, 1, MCOperand::createReg(BaseReg)); in generateLEATemplatesCommon()
293 RestrictDestRegs(BaseReg, IndexReg, PossibleDestRegsNow); in generateLEATemplatesCommon()
303 CT.Config = formatv("{3}(%{0}, %{1}, {2})", RegInfo.getName(BaseReg), in generateLEATemplatesCommon()
341 [this](unsigned BaseReg, unsigned IndexReg, in generateCodeTemplates()
346 State.getRATC().getRegister(BaseReg).aliasedBits(); in generateCodeTemplates()
401 [this](unsigned BaseReg, unsigned IndexReg, in generateCodeTemplates()
405 State.getRATC().getRegister(BaseReg).aliasedBits()); in generateCodeTemplates()

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