| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64SLSHardening.cpp | 111 case AArch64::BLR: in isBLR()
285 MachineInstr &BLR = *MBBI; in ConvertBLRToBL() local
286 assert(isBLR(BLR)); in ConvertBLRToBL()
290 switch (BLR.getOpcode()) { in ConvertBLRToBL()
291 case AArch64::BLR: in ConvertBLRToBL()
294 Reg = BLR.getOperand(0).getReg(); in ConvertBLRToBL()
296 RegIsKilled = BLR.getOperand(0).isKill(); in ConvertBLRToBL()
307 DebugLoc DL = BLR.getDebugLoc(); in ConvertBLRToBL()
370 BL->copyImplicitOps(MF, BLR); in ConvertBLRToBL()
371 MF.moveCallSiteInfo(&BLR, BL); in ConvertBLRToBL()
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| H A D | AArch64SchedPredExynos.td | 27 // Identify BLR specifying the LR register as the indirect target register.
29 CheckAll<[CheckOpcode<[BLR]>,
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| H A D | AArch64KCFI.cpp | 67 case AArch64::BLR: in emitCheck()
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| H A D | AArch64AsmPrinter.cpp | 1147 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg)); in LowerPATCHPOINT()
1183 CallOpcode = AArch64::BLR; in LowerSTATEPOINT()
1504 Blr.setOpcode(AArch64::BLR); in emitInstruction()
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| H A D | AArch64SchedThunderX.td | 258 def : InstRW<[THXT8XWriteBRR], (instregex "^BLR$")>;
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| H A D | AArch64ExpandPseudoInsts.cpp | 745 unsigned Opc = CallTarget.isGlobal() ? AArch64::BL : AArch64::BLR; in expandCALL_RVMARKER()
794 unsigned Opc = CallTarget.isGlobal() ? AArch64::BL : AArch64::BLR; in expandCALL_BTI()
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| H A D | AArch64SchedExynosM3.td | 496 def : InstRW<[M3WriteBX], (instrs BLR)>;
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| H A D | AArch64SchedTSV110.td | 345 def : InstRW<[TSV110Wr_1cyc_1AB], (instrs BLR)>;
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| H A D | AArch64SchedA57.td | 141 def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
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| H A D | AArch64SchedAmpere1.td | 695 def : InstRW<[Ampere1Write_1cyc_2A], (instrs BLR)>;
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| H A D | AArch64InstrInfo.cpp | 7417 ((LastInstrOpcode == AArch64::BLR || in getOutliningCandidateInfo()
7791 if (MI.getOpcode() == AArch64::BLR || in getOutliningType()
7949 assert(Call->getOpcode() == AArch64::BLR || in buildOutlinedFrame()
8315 return AArch64::BLR; in getBLRCallOpcode()
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| H A D | AArch64SchedExynosM4.td | 594 def : InstRW<[M4WriteBX], (instrs BLR)>;
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| H A D | AArch64SchedExynosM5.td | 629 def : InstRW<[M5WriteBX], (instrs BLR)>;
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| H A D | AArch64.td | 692 "Harden against straight line speculation across BLR instructions">;
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| /openbsd-src/gnu/llvm/compiler-rt/lib/xray/ |
| H A D | xray_trampoline_AArch64.S | 45 BLR X2
98 BLR X2
149 BLR X2
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCEarlyReturn.cpp | 60 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) || in processBlock()
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| H A D | PPCReturnProtectorLowering.cpp | 218 case PPC::BLR: in opcodeIsReturn()
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| H A D | P9InstrResources.td | 1305 (instregex "BLR(8|L)?$"),
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| H A D | P10InstrResources.td | 315 …OP_TLS, BL8_NOTOC, BL8_NOTOC_RM, BL8_NOTOC_TLS, BL8_RM, BL8_TLS, BL8_TLS_, BLR, BLR8, BLRL, BL_NOP…
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| H A D | PPCFrameLowering.cpp | 1886 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) && in emitEpilogue()
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| /openbsd-src/gnu/llvm/llvm/include/llvm/Target/ |
| H A D | TargetInstrPredicate.td | 17 // CheckOpcode<[BLR]>,
26 // whose opcode is BLR, and whose first operand is a register different from
45 // MI->getOpcode() == AArch64::BLR &&
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| /openbsd-src/gnu/usr.bin/binutils-2.17/bfd/ |
| H A D | elf64-ppc.c | 189 #define BLR 0x4e800020 /* blr */ macro
5433 bfd_put_32 (abfd, BLR, p); in savegpr0_tail()
5457 bfd_put_32 (abfd, BLR, p); in restgpr0_tail()
5472 bfd_put_32 (abfd, BLR, p); in savegpr1_tail()
5487 bfd_put_32 (abfd, BLR, p); in restgpr1_tail()
5504 bfd_put_32 (abfd, BLR, p); in savefpr0_tail()
5528 bfd_put_32 (abfd, BLR, p); in restfpr0_tail()
5536 bfd_put_32 (abfd, BLR, p); in savefpr1_tail()
5544 bfd_put_32 (abfd, BLR, p); in restfpr1_tail()
5561 bfd_put_32 (abfd, BLR, p); in savevr_tail()
[all …]
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| /openbsd-src/sys/arch/hppa/hppa/ |
| H A D | db_disasm.c | 540 #define BLR 0x3a, 0x02, 16, 3 /* BRANCH and LINK REGISTER */ macro
1018 { BLR, 0, "blr", brDasm },
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| /openbsd-src/gnu/usr.bin/gcc/gcc/config/i370/ |
| H A D | i370.md | 4009 return \"L 14,=A(%l0)\;BLR 14\";
4036 return \"L 14,=A(%l0)\;BLR 14\";
4309 return \"L 14,=A(%l0)\;BLR 14\";
4332 return \"L 14,=A(%l0)\;BLR 14\";
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| /openbsd-src/gnu/usr.bin/binutils/bfd/ |
| H A D | elf64-ppc.c | 174 #define BLR 0x4e800020 /* blr */ macro
4539 bfd_put_32 (htab->elf.dynobj, BLR, p); in ppc64_elf_func_desc_adjust()
4553 bfd_put_32 (htab->elf.dynobj, BLR, p); in ppc64_elf_func_desc_adjust()
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