Searched refs:AddSubOpc (Results 1 – 5 of 5) sorted by relevance
| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 68 unsigned MulOpc, unsigned AddSubOpc,
270 unsigned MulOpc, unsigned AddSubOpc, in ExpandFPMLxInstruction() argument
285 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
354 unsigned MulOpc, AddSubOpc; in ExpandFPMLxInstructions() local
357 MulOpc, AddSubOpc, NegAcc, HasLane) || in ExpandFPMLxInstructions()
361 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane); in ExpandFPMLxInstructions()
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| H A D | ARMBaseInstrInfo.h | 508 unsigned &AddSubOpc, bool &NegAcc,
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| H A D | ARMBaseInstrInfo.cpp | 87 uint16_t AddSubOpc; // Expanded add / sub opcode member
121 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); in ARMBaseInstrInfo()
5008 unsigned &AddSubOpc, in isFpMLxInstruction() argument
5016 AddSubOpc = Entry.AddSubOpc; in isFpMLxInstruction()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 173 unsigned ShiftAmt, AddSubOpc; in matchAArch64MulConstCombine() local
187 AddSubOpc = TargetOpcode::G_ADD; in matchAArch64MulConstCombine()
190 AddSubOpc = TargetOpcode::G_SUB; in matchAArch64MulConstCombine()
200 AddSubOpc = TargetOpcode::G_SUB; in matchAArch64MulConstCombine()
204 AddSubOpc = TargetOpcode::G_ADD; in matchAArch64MulConstCombine()
219 auto Res = B.buildInstr(AddSubOpc, {Ty}, {AddSubLHS, AddSubRHS}); in matchAArch64MulConstCombine()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 15571 unsigned AddSubOpc; in performMulCombine() local
15574 AddSubOpc = V->getOpcode(); in performMulCombine()
15575 if ((AddSubOpc == ISD::ADD || AddSubOpc == ISD::SUB) && V->hasOneUse()) { in performMulCombine()
15578 if (AddSubOpc == ISD::SUB) in performMulCombine()
15588 return DAG.getNode(AddSubOpc, DL, VT, N1, MulVal); in performMulCombine()
15593 return DAG.getNode(AddSubOpc, DL, VT, N0, MulVal); in performMulCombine()
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