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/openbsd-src/gnu/usr.bin/binutils/gas/doc/
H A Dc-arc.texi7 @node ARC-Dependent
8 @chapter ARC Dependent Features
13 @chapter ARC Dependent Features
18 @cindex ARC support
20 * ARC Options:: Options
21 * ARC Syntax:: Syntax
22 * ARC Floating Point:: Floating Point
23 * ARC Directives:: ARC Machine Directives
24 * ARC Opcodes:: Opcodes
28 @node ARC Options
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/openbsd-src/gnu/llvm/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp66 AdjOp = Positive ? ARC::ADD_rru6 : ARC::SUB_rru6; in generateStackAdjustment()
68 AdjOp = Positive ? ARC::ADD_rrs12 : ARC::SUB_rrs12; in generateStackAdjustment()
70 AdjOp = Positive ? ARC::ADD_rrlimm : ARC::SUB_rrlimm; in generateStackAdjustment()
80 assert(Reg.getReg() >= ARC::R13 && Reg.getReg() <= ARC::R25 && in determineLastCalleeSave()
93 SavedRegs.set(ARC::BLINK); in determineCalleeSaves()
109 ScalarAlloc, ARC::SP); in adjustStackToMatchRecords()
137 unsigned Opc = ARC::SUB_rrlimm; in emitPrologue()
139 Opc = ARC::SUB_rru6; in emitPrologue()
141 Opc = ARC::SUB_rrs12; in emitPrologue()
142 BuildMI(MBB, MBBI, dl, TII->get(Opc), ARC::SP) in emitPrologue()
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H A DARCRegisterInfo.cpp48 if (MI.getOpcode() == ARC::LD_rs9 && (Offset >= 256 || Offset < -256)) { in replaceFrameIndex()
50 BuildMI(MBB, II, DL, TII.get(ARC::LD_rlimm), Reg) in replaceFrameIndex()
58 if (MI.getOpcode() != ARC::GETFI && (Offset >= 256 || Offset < -256)) { in replaceFrameIndex()
60 BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass); in replaceFrameIndex()
66 BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); in replaceFrameIndex()
74 unsigned AddOpc = isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm; in replaceFrameIndex()
83 case ARC::LD_rs9: in replaceFrameIndex()
86 case ARC::LDH_rs9: in replaceFrameIndex()
87 case ARC::LDH_X_rs9: in replaceFrameIndex()
90 case ARC::LDB_rs9: in replaceFrameIndex()
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H A DARCExpandPseudos.cpp51 case ARC::ST_FAR: in getMappedOp()
52 return ARC::ST_rs9; in getMappedOp()
53 case ARC::STH_FAR: in getMappedOp()
54 return ARC::STH_rs9; in getMappedOp()
55 case ARC::STB_FAR: in getMappedOp()
56 return ARC::STB_rs9; in getMappedOp()
65 Register AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandStore()
67 isUInt<6>(SI.getOperand(2).getImm()) ? ARC::ADD_rru6 : ARC::ADD_rrlimm; in expandStore()
90 Register Ra = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTLZ()
91 Register Rb = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTLZ()
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H A DARCInstrInfo.cpp47 : ARCGenInstrInfo(ARC::ADJCALLSTACKDOWN, ARC::ADJCALLSTACKUP), RI(ST) {} in ARCInstrInfo()
54 return Opcode == ARC::LD_rs9 || Opcode == ARC::LDH_rs9 || in isLoad()
55 Opcode == ARC::LDB_rs9; in isLoad()
59 return Opcode == ARC::ST_rs9 || Opcode == ARC::STH_rs9 || in isStore()
60 Opcode == ARC::STB_rs9; in isStore()
137 static bool isUncondBranchOpcode(int Opc) { return Opc == ARC::BR; } in isUncondBranchOpcode()
140 return Opc == ARC::BRcc_rr_p || Opc == ARC::BRcc_ru6_p; in isCondBranchOpcode()
143 static bool isJumpOpcode(int Opc) { return Opc == ARC::J; } in isJumpOpcode()
285 assert(ARC::GPR32RegClass.contains(SrcReg) && in copyPhysReg()
287 assert(ARC::GPR32RegClass.contains(DestReg) && in copyPhysReg()
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H A DARCBranchFinalize.cpp96 return !(MI->getOpcode() != ARC::BRcc_rr_p && in isBRccPseudo()
97 MI->getOpcode() != ARC::BRcc_ru6_p); in isBRccPseudo()
102 if (MI->getOpcode() == ARC::BRcc_rr_p) in getBRccForPseudo()
103 return ARC::BRcc_rr; in getBRccForPseudo()
104 return ARC::BRcc_ru6; in getBRccForPseudo()
109 if (MI->getOpcode() == ARC::BRcc_rr_p) in getCmpForPseudo()
110 return ARC::CMP_rr; in getCmpForPseudo()
111 return ARC::CMP_ru6; in getCmpForPseudo()
137 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(ARC::Bcc)) in replaceWithCmpBcc()
H A DARCRegisterInfo.td1 //===- ARCRegisterInfo.td - ARC Register defs --------------*- tablegen -*-===//
10 // Declarations that describe the ARC register file
15 let Namespace = "ARC";
60 def STATUS32 : Aux<10, "status32">; // No DwarfRegNum defined in the ARC ABI
63 def GPR32: RegisterClass<"ARC", [i32], 32,
75 def SREG : RegisterClass<"ARC", [i32], 1, (add STATUS32)>;
77 def GPR_S : RegisterClass<"ARC", [i32], 8,
H A DARC.td1 //===- ARC.td - Describe the ARC Target Machine ------------*- tablegen -*-===//
12 // ARC Subtarget features
34 def ARC : Target {
H A DARCCallingConv.td1 //===- ARCCallingConv.td - Calling Conventions for ARC -----*- tablegen -*-===//
8 // This describes the calling conventions for ARC architecture.
12 // ARC Return Value Calling Convention
25 // ARC Argument Calling Conventions
H A DCMakeLists.txt1 add_llvm_component_group(ARC)
3 set(LLVM_TARGET_DEFINITIONS ARC.td)
45 ARC
H A DARCISelLowering.cpp100 addRegisterClass(MVT::i32, &ARC::GPR32RegClass); in ARCTargetLowering()
105 setStackPointerRegisterToSaveRestore(ARC::SP); in ARCTargetLowering()
327 StackPtr = DAG.getCopyFromReg(Chain, dl, ARC::SP, in LowerCall()
436 SDValue StackPtr = DAG.getRegister(ARC::SP, MVT::i32); in lowerCallResult()
529 unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass); in LowerCallArguments()
557 static const MCPhysReg ArgRegs[] = {ARC::R0, ARC::R1, ARC::R2, ARC::R3, in LowerCallArguments()
558 ARC::R4, ARC::R5, ARC::R6, ARC::R7}; in LowerCallArguments()
573 unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass); in LowerCallArguments()
H A DARCOptAddrMode.cpp137 case ARC::SUB_rru6: in isAddConstantOp()
140 case ARC::ADD_rru6: in isAddConstantOp()
264 int NewOpcode = ARC::getPostIncOpcode(Ldst.getOpcode()); in tryToCombine()
486 if (ARC::getPostIncOpcode(MI->getOpcode()) < 0) in processBasicBlock()
H A DARCISelDAGToDAG.cpp175 isInt<12>(CVal) ? ARC::MOV_rs12 : ARC::MOV_rlimm, in Select()
/openbsd-src/gnu/usr.bin/binutils-2.17/gas/doc/
H A Dc-arc.texi7 @node ARC-Dependent
8 @chapter ARC Dependent Features
13 @chapter ARC Dependent Features
18 @cindex ARC support
20 * ARC Options:: Options
21 * ARC Syntax:: Syntax
22 * ARC Floating Point:: Floating Point
23 * ARC Directives:: ARC Machine Directives
24 * ARC Opcodes:: Opcodes
28 @node ARC Options
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/openbsd-src/gnu/llvm/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp125 ARC::R0, ARC::R1, ARC::R2, ARC::R3, ARC::R4, ARC::R5, ARC::R6,
126 ARC::R7, ARC::R8, ARC::R9, ARC::R10, ARC::R11, ARC::R12, ARC::R13,
127 ARC::R14, ARC::R15, ARC::R16, ARC::R17, ARC::R18, ARC::R19, ARC::R20,
128 ARC::R21, ARC::R22, ARC::R23, ARC::R24, ARC::R25, ARC::GP, ARC::FP,
129 ARC::SP, ARC::ILINK, ARC::R30, ARC::BLINK};
H A DCMakeLists.txt10 ARC
/openbsd-src/gnu/usr.bin/binutils-2.17/bfd/
H A Dcpu-arc.c25 #define ARC(mach, print_name, default_p, next) \ macro
43 ARC ( bfd_mach_arc_5, "arc5", FALSE, &arch_info_struct[1] ),
44 ARC ( bfd_mach_arc_5, "base", FALSE, &arch_info_struct[2] ),
45 ARC ( bfd_mach_arc_6, "arc6", FALSE, &arch_info_struct[3] ),
46 ARC ( bfd_mach_arc_7, "arc7", FALSE, &arch_info_struct[4] ),
47 ARC ( bfd_mach_arc_8, "arc8", FALSE, NULL ),
51 ARC ( bfd_mach_arc_6, "arc", TRUE, &arch_info_struct[0] );
/openbsd-src/gnu/usr.bin/binutils/bfd/
H A Dcpu-arc.c25 #define ARC(mach, print_name, default_p, next) \ macro
43 ARC ( bfd_mach_arc_5, "arc5", FALSE, &arch_info_struct[1] ),
44 ARC ( bfd_mach_arc_5, "base", FALSE, &arch_info_struct[2] ),
45 ARC ( bfd_mach_arc_6, "arc6", FALSE, &arch_info_struct[3] ),
46 ARC ( bfd_mach_arc_7, "arc7", FALSE, &arch_info_struct[4] ),
47 ARC ( bfd_mach_arc_8, "arc8", FALSE, NULL ),
51 ARC ( bfd_mach_arc_6, "arc", TRUE, &arch_info_struct[0] );
/openbsd-src/gnu/llvm/clang/docs/
H A DAutomaticReferenceCounting.rst62 Objective-C Automatic Reference Counting (ARC)
83 The secondary purpose is to act as a rationale for why ARC was designed in this
184 ARC is under continual evolution, and this document must be updated as the
191 ARC applies to Objective-C pointer types, block pointer types, and
218 ARC may be explicitly enabled with the compiler flag ``-fobjc-arc``. It may
222 If ARC is enabled, ``__has_feature(objc_arc)`` will expand to 1 in the
232 the restrictions imposed on their use under ARC. Note in particular that it
247 ARC's semantics and restrictions.
251 We are not at liberty to require all code to be recompiled with ARC;
252 therefore, ARC must interoperate with Objective-C code which manages retains
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/openbsd-src/gnu/llvm/llvm/lib/Target/ARC/MCTargetDesc/
H A DARCMCTargetDesc.cpp46 InitARCMCRegisterInfo(X, ARC::BLINK); in createARCMCRegisterInfo()
61 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, ARC::SP, 0); in createARCMCAsmInfo()
H A DCMakeLists.txt12 ARC
/openbsd-src/gnu/gcc/gcc/config/arc/
H A Darc.opt1 ; Options for the Argonaut ARC port of the compiler
43 -mcpu=CPU Compile code for ARC variant CPU
/openbsd-src/gnu/llvm/llvm/lib/Target/ARC/TargetInfo/
H A DCMakeLists.txt9 ARC
/openbsd-src/gnu/llvm/lldb/source/Plugins/ABI/
H A DCMakeLists.txt1 foreach(target AArch64 ARM ARC Hexagon Mips PowerPC SystemZ X86)
/openbsd-src/gnu/llvm/llvm/utils/gn/secondary/llvm/lib/Target/
H A Dtargets_with_asm_parsers.gni6 if (target != "ARC" && target != "NVPTX" && target != "XCore") {

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