Home
last modified time | relevance | path

Searched refs:AR (Results 1 – 25 of 347) sorted by relevance

12345678910>>...14

/openbsd-src/gnu/llvm/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.td24 : RRR_Inst<0x00, oper1, oper2, (outs AR:$r), (ins AR:$s, AR:$t),
26 [(set AR:$r, (opNode AR:$s, AR:$t))]> {
38 : RRR_Inst<0x00, 0x00, oper, (outs AR:$r), (ins AR:$s, AR:$t),
41 def ADDX2 : ADDX<0x09, "addx2", [(set AR:$r, (add AR:$t, (shl AR:$s, (i32 1))))]>;
42 def ADDX4 : ADDX<0x0A, "addx4", [(set AR:$r, (add AR:$t, (shl AR:$s, (i32 2))))]>;
43 def ADDX8 : ADDX<0x0B, "addx8", [(set AR:$r, (add AR:$t, (shl AR:$s, (i32 3))))]>;
46 : RRR_Inst<0x00, 0x00, oper, (outs AR:$r), (ins AR:$s, AR:$t),
49 def SUBX2 : SUBX<0x0D, "subx2", [(set AR:$r, (sub (shl AR:$s, (i32 1)), AR:$t))]>;
50 def SUBX4 : SUBX<0x0E, "subx4", [(set AR:$r, (sub (shl AR:$s, (i32 2)), AR:$t))]>;
51 def SUBX8 : SUBX<0x0F, "subx8", [(set AR:$r, (sub (shl AR:$s, (i32 3)), AR:$t))]>;
[all …]
/openbsd-src/gnu/usr.bin/binutils/opcodes/
H A Dia64-waw.tbl3 AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ret, c…
4 AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, loadrs, flushrs, IC:mov-to-AR-B…
5 AR[CCV]; IC:mov-to-AR-CCV; IC:mov-to-AR-CCV; impliedF
6 AR[CFLG]; IC:mov-to-AR-CFLG; IC:mov-to-AR-CFLG; impliedF
7 AR[CSD]; ld16, IC:mov-to-AR-CSD; ld16, IC:mov-to-AR-CSD; impliedF
8 AR[EC]; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; impli…
9 AR[EFLAG]; mov-to-AR-EFLAG; mov-to-AR-EFLAG; impliedF
10 AR[FCR]; mov-to-AR-FCR; mov-to-AR-FCR; impliedF
11 AR[FDR]; mov-to-AR-FDR; mov-to-AR-FDR; impliedF
12 AR[FIR]; mov-to-AR-FIR; mov-to-AR-FIR; impliedF
[all …]
H A Dia64-ic.tbl25 …C:mem-writers, chk.s, cmp, cmp4, fc, itc.i, itc.d, itr.i, itr.d, IC:mov-to-AR-gr, IC:mov-to-BR, IC…
27 gr-writers; alloc, dep, getf, IC:gr-readers-writers, IC:mem-readers-int, IC:mov-from-AR, IC:mov-fro…
70 mov-from-AR; IC:mov-from-AR-M, IC:mov-from-AR-I, IC:mov-from-AR-IM
71 mov-from-AR-BSP; IC:mov-from-AR-M[Field(ar3) == BSP]
72 mov-from-AR-BSPSTORE; IC:mov-from-AR-M[Field(ar3) == BSPSTORE]
73 mov-from-AR-CCV; IC:mov-from-AR-M[Field(ar3) == CCV]
74 mov-from-AR-CFLG; IC:mov-from-AR-M[Field(ar3) == CFLG]
75 mov-from-AR-CSD; IC:mov-from-AR-M[Field(ar3) == CSD]
76 mov-from-AR-EC; IC:mov-from-AR-I[Field(ar3) == EC]
77 mov-from-AR-EFLAG; IC:mov-from-AR-M[Field(ar3) == EFLAG]
[all …]
H A Dia64-raw.tbl3 AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ia, br…
4 AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, br.ia, flushrs, IC:mov-from-AR-…
5 AR[CFLG]; IC:mov-to-AR-CFLG; br.ia, IC:mov-from-AR-CFLG; impliedF
6 AR[CCV]; IC:mov-to-AR-CCV; br.ia, IC:cmpxchg, IC:mov-from-AR-CCV; impliedF
7 AR[CSD]; ld16, IC:mov-to-AR-CSD; br.ia, cmp8xchg16, IC:mov-from-AR-CSD, st16; impliedF
8 AR[EC]; IC:mod-sched-brs, br.ret, IC:mov-to-AR-EC; br.call, brl.call, br.ia, IC:mod-sched-brs, IC:m…
9 AR[EFLAG]; IC:mov-to-AR-EFLAG; br.ia, IC:mov-from-AR-EFLAG; impliedF
10 AR[FCR]; IC:mov-to-AR-FCR; br.ia, IC:mov-from-AR-FCR; impliedF
11 AR[FDR]; IC:mov-to-AR-FDR; br.ia, IC:mov-from-AR-FDR; impliedF
12 AR[FIR]; IC:mov-to-AR-FIR; br.ia, IC:mov-from-AR-FIR; impliedF
[all …]
/openbsd-src/gnu/usr.bin/binutils-2.17/opcodes/
H A Dia64-waw.tbl3 AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ret, c…
4 AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, loadrs, flushrs, IC:mov-to-AR-B…
5 AR[CCV]; IC:mov-to-AR-CCV; IC:mov-to-AR-CCV; impliedF
6 AR[CFLG]; IC:mov-to-AR-CFLG; IC:mov-to-AR-CFLG; impliedF
7 AR[CSD]; ld16, IC:mov-to-AR-CSD; ld16, IC:mov-to-AR-CSD; impliedF
8 AR[EC]; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; impli…
9 AR[EFLAG]; IC:mov-to-AR-EFLAG; IC:mov-to-AR-EFLAG; impliedF
10 AR[FCR]; IC:mov-to-AR-FCR; IC:mov-to-AR-FCR; impliedF
11 AR[FDR]; IC:mov-to-AR-FDR; IC:mov-to-AR-FDR; impliedF
12 AR[FIR]; IC:mov-to-AR-FIR; IC:mov-to-AR-FIR; impliedF
[all …]
H A Dia64-ic.tbl25 …C:mem-writers, chk.s, cmp, cmp4, fc, itc.i, itc.d, itr.i, itr.d, IC:mov-to-AR-gr, IC:mov-to-BR, IC…
27 gr-writers; alloc, dep, getf, IC:gr-readers-writers, IC:mem-readers-int, IC:mov-from-AR, IC:mov-fro…
70 mov-from-AR; IC:mov-from-AR-M, IC:mov-from-AR-I, IC:mov-from-AR-IM
71 mov-from-AR-BSP; IC:mov-from-AR-M[Field(ar3) == BSP]
72 mov-from-AR-BSPSTORE; IC:mov-from-AR-M[Field(ar3) == BSPSTORE]
73 mov-from-AR-CCV; IC:mov-from-AR-M[Field(ar3) == CCV]
74 mov-from-AR-CFLG; IC:mov-from-AR-M[Field(ar3) == CFLG]
75 mov-from-AR-CSD; IC:mov-from-AR-M[Field(ar3) == CSD]
76 mov-from-AR-EC; IC:mov-from-AR-I[Field(ar3) == EC]
77 mov-from-AR-EFLAG; IC:mov-from-AR-M[Field(ar3) == EFLAG]
[all …]
H A Dia64-raw.tbl3 AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ia, br…
4 AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, br.ia, flushrs, IC:mov-from-AR-…
5 AR[CCV]; IC:mov-to-AR-CCV; br.ia, IC:cmpxchg, IC:mov-from-AR-CCV; impliedF
6 AR[CFLG]; IC:mov-to-AR-CFLG; br.ia, IC:mov-from-AR-CFLG; impliedF
7 AR[CSD]; ld16, IC:mov-to-AR-CSD; br.ia, cmp8xchg16, IC:mov-from-AR-CSD, st16; impliedF
8 AR[EC]; IC:mod-sched-brs, br.ret, IC:mov-to-AR-EC; br.call, brl.call, br.ia, IC:mod-sched-brs, IC:m…
9 AR[EFLAG]; IC:mov-to-AR-EFLAG; br.ia, IC:mov-from-AR-EFLAG; impliedF
10 AR[FCR]; IC:mov-to-AR-FCR; br.ia, IC:mov-from-AR-FCR; impliedF
11 AR[FDR]; IC:mov-to-AR-FDR; br.ia, IC:mov-from-AR-FDR; impliedF
12 AR[FIR]; IC:mov-to-AR-FIR; br.ia, IC:mov-from-AR-FIR; impliedF
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Analysis/
H A DIVUsers.cpp37 LoopStandardAnalysisResults &AR) { in run() argument
38 return IVUsers(&L, &AR.AC, &AR.LI, &AR.DT, &AR.SE); in run()
59 if (const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(S)) { in isInteresting() local
62 if (AR->getLoop() == L) in isInteresting()
63 return AR->isAffine() || in isInteresting()
65 SE->getSCEVAtScope(AR, LI->getLoopFor(I->getParent())) != AR); in isInteresting()
69 return isInteresting(AR->getStart(), I, L, SE, LI) && in isInteresting()
70 !isInteresting(AR->getStepRecurrence(*SE), I, L, SE, LI); in isInteresting()
211 auto NormalizePred = [&](const SCEVAddRecExpr *AR) { in AddUsersIfInteresting() argument
212 auto *L = AR->getLoop(); in AddUsersIfInteresting()
[all …]
H A DLoopCacheAnalysis.cpp83 const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(&AccessFn); in isOneDimensionalArray() local
84 if (!AR || !AR->isAffine()) in isOneDimensionalArray()
87 assert(AR->getLoop() && "AR should have a loop"); in isOneDimensionalArray()
90 const SCEV *Start = AR->getStart(); in isOneDimensionalArray()
91 const SCEV *Step = AR->getStepRecurrence(SE); in isOneDimensionalArray()
99 const SCEV *StepRec = AR->getStepRecurrence(SE); in isOneDimensionalArray()
321 const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(getSubscript(I)); in computeRefCost() local
322 assert(AR && AR->getLoop() && "Expecting valid loop"); in computeRefCost()
324 computeTripCount(*AR->getLoop(), *Sizes.back(), SE); in computeRefCost()
498 const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(getSubscript(Idx)); in getSubscriptIndex() local
[all …]
H A DAliasAnalysisEvaluator.cpp37 static void PrintResults(AliasResult AR, bool P, in PrintResults() argument
57 AR.swap(); in PrintResults()
59 errs() << " " << AR << ":\t"; in PrintResults()
90 static inline void PrintLoadStoreResults(AliasResult AR, bool P, in PrintLoadStoreResults() argument
94 errs() << " " << AR << ": " << *V1 << " <-> " << *V2 << '\n'; in PrintLoadStoreResults()
136 AliasResult AR = AA.alias(I1->first, Size1, I2->first, Size2); in runInternal() local
137 switch (AR) { in runInternal()
139 PrintResults(AR, PrintNoAlias, *I1, *I2, F.getParent()); in runInternal()
143 PrintResults(AR, PrintMayAlias, *I1, *I2, F.getParent()); in runInternal()
147 PrintResults(AR, PrintPartialAlias, *I1, *I2, F.getParent()); in runInternal()
[all …]
H A DScalarEvolutionNormalization.cpp48 NormalizeDenormalizeRewriter::visitAddRecExpr(const SCEVAddRecExpr *AR) { in visitAddRecExpr() argument
51 transform(AR->operands(), std::back_inserter(Operands), in visitAddRecExpr()
54 if (!Pred(AR)) in visitAddRecExpr()
55 return SE.getAddRecExpr(Operands, AR->getLoop(), SCEV::FlagAnyWrap); in visitAddRecExpr()
94 return SE.getAddRecExpr(Operands, AR->getLoop(), SCEV::FlagAnyWrap); in visitAddRecExpr()
100 auto Pred = [&](const SCEVAddRecExpr *AR) { in normalizeForPostIncUse() argument
101 return Loops.count(AR->getLoop()); in normalizeForPostIncUse()
114 auto Pred = [&](const SCEVAddRecExpr *AR) { in denormalizeForPostIncUse() argument
115 return Loops.count(AR->getLoop()); in denormalizeForPostIncUse()
H A DAliasAnalysis.cpp406 raw_ostream &llvm::operator<<(raw_ostream &OS, AliasResult AR) { in operator <<() argument
407 switch (AR) { in operator <<()
419 if (AR.hasOffset()) in operator <<()
420 OS << " (off " << AR.getOffset() << ")"; in operator <<()
476 AliasResult AR = alias(MemoryLocation::get(L), Loc, AAQI, L); in getModRefInfo() local
477 if (AR == AliasResult::NoAlias) in getModRefInfo()
492 AliasResult AR = alias(MemoryLocation::get(S), Loc, AAQI, S); in getModRefInfo() local
495 if (AR == AliasResult::NoAlias) in getModRefInfo()
525 AliasResult AR = alias(MemoryLocation::get(V), Loc, AAQI, V); in getModRefInfo() local
528 if (AR == AliasResult::NoAlias) in getModRefInfo()
[all …]
H A DDDG.cpp309 LoopStandardAnalysisResults &AR) { in run() argument
311 DependenceInfo DI(F, &AR.AA, &AR.SE, &AR.LI); in run()
312 return std::make_unique<DataDependenceGraph>(L, AR.LI, DI); in run()
317 LoopStandardAnalysisResults &AR, in run() argument
320 OS << *AM.getResult<DDGAnalysis>(L, AR); in run()
H A DScalarEvolution.cpp303 const SCEVAddRecExpr *AR = cast<SCEVAddRecExpr>(this); in print() local
304 OS << "{" << *AR->getOperand(0); in print()
305 for (unsigned i = 1, e = AR->getNumOperands(); i != e; ++i) in print()
306 OS << ",+," << *AR->getOperand(i); in print()
308 if (AR->hasNoUnsignedWrap()) in print()
310 if (AR->hasNoSignedWrap()) in print()
312 if (AR->hasNoSelfWrap() && in print()
313 !AR->getNoWrapFlags((NoWrapFlags)(FlagNUW | FlagNSW))) in print()
315 AR->getLoop()->getHeader()->printAsOperand(OS, /*PrintType=*/false); in print()
1385 static const SCEV *getPreStartForExtend(const SCEVAddRecExpr *AR, Type *Ty, in getPreStartForExtend() argument
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Transforms/Scalar/
H A DLoopRotation.cpp47 LoopStandardAnalysisResults &AR, in run() argument
57 const SimplifyQuery SQ = getBestSimplifyQuery(AR, DL); in run()
60 if (AR.MSSA) in run()
61 MSSAU = MemorySSAUpdater(AR.MSSA); in run()
62 bool Changed = LoopRotation(&L, &AR.LI, &AR.TTI, &AR.AC, &AR.DT, &AR.SE, in run()
69 if (AR.MSSA && VerifyMemorySSA) in run()
70 AR.MSSA->verifyMemorySSA(); in run()
73 if (AR.MSSA) in run()
H A DLoopInstSimplify.cpp216 LoopStandardAnalysisResults &AR, in run() argument
219 if (AR.MSSA) { in run()
220 MSSAU = MemorySSAUpdater(AR.MSSA); in run()
222 AR.MSSA->verifyMemorySSA(); in run()
224 if (!simplifyLoopInst(L, AR.DT, AR.LI, AR.AC, AR.TLI, in run()
230 if (AR.MSSA) in run()
H A DLoopPassManager.cpp28 LoopStandardAnalysisResults &AR, LPMUpdater &U) { in run() argument
31 ? runWithLoopNestPasses(L, AM, AR, U) in run()
32 : runWithoutLoopNestPasses(L, AM, AR, U); in run()
69 LoopStandardAnalysisResults &AR, in runWithLoopNestPasses() argument
77 PassInstrumentation PI = AM.getResult<PassInstrumentationAnalysis>(L, AR); in runWithLoopNestPasses()
94 PassPA = runSinglePass(L, Pass, AM, AR, U, PI); in runWithLoopNestPasses()
108 LoopNestPtr = LoopNest::getLoopNest(*OuterMostLoop, AR.SE); in runWithLoopNestPasses()
113 PassPA = runSinglePass(*LoopNestPtr, Pass, AM, AR, U, PI); in runWithLoopNestPasses()
152 LoopStandardAnalysisResults &AR, in runWithoutLoopNestPasses() argument
158 PassInstrumentation PI = AM.getResult<PassInstrumentationAnalysis>(L, AR); in runWithoutLoopNestPasses()
[all …]
H A DLoopDeletion.cpp512 LoopStandardAnalysisResults &AR, in run() argument
522 auto Result = deleteLoopIfDead(&L, AR.DT, AR.SE, AR.LI, AR.MSSA, ORE); in run()
528 Result = merge(Result, breakBackedgeIfNotTaken(&L, AR.DT, AR.SE, AR.LI, in run()
529 AR.MSSA, ORE)); in run()
538 if (AR.MSSA) in run()
H A DLoopUnrollAndJamPass.cpp535 LoopStandardAnalysisResults &AR, in run() argument
539 DependenceInfo DI(&F, &AR.AA, &AR.SE, &AR.LI); in run()
542 if (!tryToUnrollAndJamLoop(LN, AR.DT, AR.LI, AR.SE, AR.TTI, AR.AC, DI, ORE, in run()
/openbsd-src/gnu/usr.bin/binutils/
H A DMakefile.in215 AR = @AR@
255 echo $(AR); \
628 $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
651 $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
673 $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
695 $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
717 $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
739 $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
761 $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
783 $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
[all …]
/openbsd-src/share/mk/
H A Dsys.mk19 AR?= ar
90 ${AR} ${ARFLAGS} $@ $*.o
100 ${AR} ${ARFLAGS} $@ $*.o
109 ${AR} ${ARFLAGS} $@ $*.o
118 ${AR} ${ARFLAGS} $@ $*.o
127 ${AR} ${ARFLAGS} $@ $*.o
137 ${AR} ${ARFLAGS} $@ $*.o
146 ${AR} ${ARFLAGS} $@ $*.o
155 ${AR} ${ARFLAGS} $@ $*.o
165 ${AR}
[all...]
/openbsd-src/gnu/usr.bin/binutils-2.17/
H A DMakefile.in112 AR="$(AR_FOR_BUILD)"; export AR; \
146 AR="$(AR)"; export AR; \
191 AR="$(AR_FOR_TARGET)"; export AR; \
275 AR = @AR@
2802 $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
2828 $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
2854 $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
2880 $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
2907 $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
2934 $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
[all …]
/openbsd-src/gnu/llvm/compiler-rt/lib/sanitizer_common/symbolizer/scripts/
H A Dbuild_symbolizer.sh58 AR=$CLANG_DIR/llvm-ar
61 for F in $CC $CXX $TBLGEN $LINK $OPT $AR; do
86 AR="${AR}" CC="${CC}" CFLAGS="$FLAGS -Wno-deprecated-non-prototype" RANLIB=/bin/true ./configure --…
144 $AR rc symbolizer.a sanitizer_symbolize.o sanitizer_wrappers.o
197 $AR rcs $A symbolizer.o
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonVExtract.cpp107 Register AR = in runOnMachineFunction() local
125 unsigned FiOpc = AR != 0 ? Hexagon::PS_fia : Hexagon::PS_fi; in runOnMachineFunction()
127 if (AR) in runOnMachineFunction()
128 MIB.addReg(AR); in runOnMachineFunction()
181 if (AR && MaxAlign) { in runOnMachineFunction()
183 MachineInstr *AlignaI = MRI.getVRegDef(AR); in runOnMachineFunction()
/openbsd-src/gnu/llvm/clang/lib/Sema/
H A DDelayedDiagnostic.cpp24 DelayedDiagnostic::makeAvailability(AvailabilityResult AR, in makeAvailability() argument
54 DD.AvailabilityData.AR = AR; in makeAvailability()

12345678910>>...14