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Searched refs:ALU (Results 1 – 25 of 90) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsSchedule.td12 def ALU : FuncUnit;
388 def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
389 InstrItinData<IIM16Alu , [InstrStage<1, [ALU]>]>,
390 InstrItinData<II_ADDI , [InstrStage<1, [ALU]>]>,
391 InstrItinData<II_ADDIU , [InstrStage<1, [ALU]>]>,
392 InstrItinData<II_ADDIUPC , [InstrStage<1, [ALU]>]>,
393 InstrItinData<II_ADD , [InstrStage<1, [ALU]>]>,
394 InstrItinData<II_ADDU , [InstrStage<1, [ALU]>]>,
395 InstrItinData<II_AUI , [InstrStage<1, [ALU]>]>,
396 InstrItinData<II_AND , [InstrStage<1, [ALU]>]>,
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/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td25 // - Four ALU (Fixed Point Arithmetic) units. One on each slice. P9_ALU_*
33 // Two cycle ALU vector operation that uses an entire superslice.
34 // Uses both ALU units (the even ALUE and odd ALUO units), two pipelines
86 // Restricted Dispatch ALU operation for 3 cycles. The operation runs on a
104 // Standard Dispatch ALU operation for 3 cycles. Only one slice used.
121 // Standard Dispatch ALU operation for 2 cycles. Only one slice used.
176 // Restricted Dispatch ALU operation for 2 cycles. The operation runs on a
205 // Three cycle ALU vector operation that uses an entire superslice.
206 // Uses both ALU units (the even ALUE and odd ALUO units), two pipelines
452 // 7 cycle Restricted DP operation and one 3 cycle ALU operation.
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H A DP10InstrResources.td21 // 22 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands
41 // 26 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands
62 // 27 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands
77 // 36 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands
257 // 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands
269 // 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands
296 // 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 3 input operands
489 // 20 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands
512 // 25 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands
543 // 41 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands
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H A DPPCScheduleP9.td88 // Four ALU (Fixed Point Arithmetic) units in total. Two even, two Odd.
89 def ALU : ProcResource<4>;
91 //Even ALU pipelines
92 let Super = ALU;
95 //Odd ALU pipelines
96 let Super = ALU;
190 // ALU Units
191 // An ALU may take either 2 or 3 cycles to complete the operation.
192 // However, the ALU unit is only ever busy for 1 cycle at a time and may
194 def P9_ALU_2C : SchedWriteRes<[ALU]> {
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/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DR600Schedule.td10 // slots ALU.X, ALU.Y, ALU.Z, ALU.W, and TRANS. For cayman cards, the TRANS
H A DAMDGPUIGroupLP.cpp68 ALU = 1u << 0, enumerator
78 ALL = ALU | VALU | SALU | MFMA | VMEM | VMEM_READ | VMEM_WRITE | DS |
850 else if (((SGMask & SchedGroupMask::ALU) != SchedGroupMask::NONE) && in canAddMI()
1068 if ((InvertedMask & SchedGroupMask::ALU) == SchedGroupMask::NONE) in invertSchedBarrierMask()
1075 InvertedMask &= ~SchedGroupMask::ALU; in invertSchedBarrierMask()
H A DR600Processors.td19 "Older version of ALU instructions encoding"
/openbsd-src/gnu/gcc/gcc/config/arm/
H A Darm1026ejs.md42 ;; - An Arithmetic Logic Unit (ALU) pipeline.
44 ;; The ALU pipeline has fetch, issue, decode, execute, memory, and
57 ;; ALU Instructions
60 ;; ALU instructions require three cycles to execute, and use the ALU
67 ;; ALU operations with no shifted operand
73 ;; ALU operations with a shift-by-constant operand
79 ;; ALU operations with a shift-by-register operand
159 ;; LSU instructions require six cycles to execute. They use the ALU
191 ;; The ALU pipeline is stalled until the completion of the last memory
192 ;; stage in the LSU pipeline. That is modeled by keeping the ALU
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H A Darm1136jfs.md46 ;; - A 4-stage ALU pipeline. It has shifter, ALU (main integer operations),
52 ;; The 4th-stage writeback is shared between the ALU and MAC pipelines,
59 ;; including the writeback stage, is independent from the ALU & LSU pipes.)
61 (define_cpu_unit "e_1,e_2,e_3,e_wb" "arm1136jfs") ; ALU and MAC
62 ; e_1 = Sh/Mac1, e_2 = ALU/Mac2, e_3 = SAT/Mac3
66 ;; ALU Instructions
69 ;; ALU instructions require eight cycles to execute, and use the ALU
76 ;; ALU operations with no shifted operand
82 ;; ALU operations with a shift-by-constant operand
88 ;; ALU operations with a shift-by-register operand
H A Darm926ejs.md42 ;; The ALU pipeline has fetch, decode, execute, memory, and
49 ;; ALU Instructions
52 ;; ALU instructions require three cycles to execute, and use the ALU
59 ;; ALU operations with no shifted operand
65 ;; ALU operations with a shift-by-register operand
H A Darm1020e.md42 ;; - An Arithmetic Logic Unit (ALU) pipeline.
44 ;; The ALU pipeline has fetch, issue, decode, execute, memory, and
57 ;; ALU Instructions
60 ;; ALU instructions require three cycles to execute, and use the ALU
67 ;; ALU operations with no shifted operand
73 ;; ALU operations with a shift-by-constant operand
79 ;; ALU operations with a shift-by-register operand
159 ;; LSU instructions require six cycles to execute. They use the ALU
191 ;; The ALU pipeline is decoupled after the first cycle unless there is
200 ;; As with ALU operations, if one of the destination registers is the
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td24 def WriteI : SchedWrite; // ALU
25 def WriteISReg : SchedWrite; // ALU of Shifted-Reg
26 def WriteIEReg : SchedWrite; // ALU of Extended-Reg
27 def ReadI : SchedRead; // ALU
28 def ReadISReg : SchedRead; // ALU of Shifted-Reg
29 def ReadIEReg : SchedRead; // ALU of Extended-Reg
H A DAArch64SchedA55.td44 def CortexA55UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
51 // The FP DIV/SQRT instructions execute totally differently from the FP ALU
54 def CortexA55UnitFPALU : ProcResource<2> { let BufferSize = 0; } // FP ALU
67 def : WriteRes<WriteI, [CortexA55UnitALU]> { let Latency = 3; } // ALU
68 def : WriteRes<WriteISReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Shifted-Reg
69 def : WriteRes<WriteIEReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Extended-Reg
147 // FP ALU
181 // FP ALU specific new schedwrite definitions
215 // ALU - ALU input operands are generally needed in EX1. An operand produced in
216 // in say EX2 can be forwarded for consumption to ALU in EX1, thereby
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H A DAArch64SchedA53.td42 def A53UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
47 def A53UnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU
57 // ALU - Despite having a full latency of 4, most of the ALU instructions can
125 // FP ALU
157 // ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
H A DAArch64SchedThunderX.td37 def THXT8XUnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
42 def THXT8XUnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU
51 // ALU
152 // FP ALU
200 // ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
/openbsd-src/gnu/usr.bin/binutils-2.17/cpu/
H A Dm32r.cpu796 (ALU - () "ALU")
808 ((PIPE OS) (IDOC ALU))
816 ((IDOC ALU))
831 ((PIPE OS) (IDOC ALU))
842 ((PIPE OS) (IDOC ALU))
852 ((IDOC ALU))
862 ((PIPE OS) (IDOC ALU))
1118 ((PIPE OS) (IDOC ALU))
1128 ((IDOC ALU))
1138 ((PIPE OS) (IDOC ALU))
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/openbsd-src/gnu/llvm/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td54 def ALU : ProcResource<1> { let BufferSize = 0; }
68 def : WriteRes<WriteALU, [ALU]> { let Latency = 1; }
/openbsd-src/gnu/usr.bin/gcc/gcc/config/i386/
H A Dk6.md29 ;; alu describes both ALU units (ALU-X and ALU-Y).
/openbsd-src/gnu/llvm/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td242 // ALU instructions
265 multiclass ALU<BPFArithOp Opc, string OpcodeStr, SDNode OpNode> {
290 defm ADD : ALU<BPF_ADD, "+=", add>;
291 defm SUB : ALU<BPF_SUB, "-=", sub>;
292 defm OR : ALU<BPF_OR, "|=", or>;
293 defm AND : ALU<BPF_AND, "&=", and>;
294 defm SLL : ALU<BPF_LSH, "<<=", shl>;
295 defm SRL : ALU<BPF_RSH, ">>=", srl>;
296 defm XOR : ALU<BPF_XOR, "^=", xor>;
297 defm SRA : ALU<BPF_ARSH, "s>>=", sra>;
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/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMScheduleM7.td25 // The Cortex-M7 has two ALU, two LOAD, a STORE, a MAC, a BRANCH and a VFP
35 // for scheduling, so simple ALU operations executing in EX2 will have
58 // Basic ALU with shifts.
117 // ALU operations (32/64-bit). These go down the FP pipeline.
188 // Assume that these will go down the main ALU pipeline.
319 // Sched definitions for ALU
322 // Shifted ALU operands are read a cycle early.
H A DARMSchedule.td44 // def P01 : ProcResource<3>; // ALU unit (3 of it).
59 // Basic ALU operation.
63 // Basic ALU with shifts.
111 // ALU operations (32/64-bit)
H A DARMScheduleV6.td227 // Single-precision FP ALU
230 // Double-precision FP ALU
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonIntrinsicsV5.td222 // ALU32/ALU
225 // ALU32 / ALU / Logical Operations.
272 // XTYPE/ALU
281 // XTYPE / ALU / Logical-logical Words.
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVSchedule.td10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
120 def ReadIALU32 : SchedRead; // 32-bit integer ALU operations on RV64I
H A DRISCVSchedRocket.td33 def RocketUnitALU : ProcResource<1>; // Int ALU
38 def RocketUnitFPALU : ProcResource<1>; // FP ALU

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