| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | MipsMachineFunction.cpp | 125 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9); in initGlobalBaseReg()
152 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg) in initGlobalBaseReg()
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| H A D | MipsInstructionSelector.cpp | 342 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
382 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select() local
386 if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI)) in select()
403 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select() local
408 if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI)) in select()
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| H A D | MipsExpandPseudo.cpp | 364 Opcode = Mips::ADDu; in expandAtomicBinOpSubword()
649 Opcode = Mips::ADDu; in expandAtomicBinOp()
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| H A D | MicroMipsSizeReduction.cpp | 222 {RT_OneInstr, OpCodes(Mips::ADDu, Mips::ADDU16_MM),
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| H A D | MipsBranchExpansion.cpp | 516 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT) in expandToLongBranch()
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| H A D | MipsScheduleP5600.td | 226 ADDu, SLLV, SRAV, SRLV, LSA, COPY)>;
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| H A D | MipsInstrInfo.td | 2077 def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
2705 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
3169 (ADDu GPR32:$lhs, GPR32:$rhs)>, ISA_MIPS1, ASE_NOT_DSP;
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| H A D | MipsFastISel.cpp | 2110 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg()); in simplifyAddress()
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| H A D | Mips64InstrInfo.td | 913 (ADDu GPR32:$src, GPR32:$src2), sub_32)>;
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| H A D | MipsScheduleGeneric.td | 47 def : InstRW<[GenericWriteALU], (instrs ADD, ADDi, ADDiu, ADDu, AND, ANDi,
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsABIInfo.cpp | 105 return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu; in GetPtrAdduOp()
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| H A D | MipsTargetStreamer.cpp | 269 emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(), in emitAddu()
342 emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI); in emitStoreWithImmOffset()
378 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in emitLoadWithImmOffset()
1201 TmpInst.setOpcode(Mips::ADDu); in emitDirectiveCpLoad()
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| H A D | MipsInstPrinter.cpp | 331 case Mips::ADDu: in printAlias()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 2731 unsigned AdduOp = !Is32BitImm ? Mips::DADDu : Mips::ADDu; in loadImmediate()
2959 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, DstReg, GPReg, in loadAndAddSymbolAddress()
3004 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, TmpReg, TmpReg, GPReg, in loadAndAddSymbolAddress()
3016 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg, in loadAndAddSymbolAddress()
3081 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg, in loadAndAddSymbolAddress()
3220 TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3778 TOut.emitRRR(ABI.ArePtrs64bit() ? Mips::DADDu : Mips::ADDu, TmpReg, in expandMem16Inst()
3835 TOut.emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in expandMem16Inst()
4828 FinalOpcode = Mips::ADDu; in expandAliasImmediate()
5188 TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, STI); in expandAbs()
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