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/netbsd-src/external/apache2/llvm/dist/llvm/docs/AMDGPU/
H A Dgfx90a_hwreg.rst50 HW_REG_HW_ID Id of wave, simd, compute unit, etc.
51 HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
52 HW_REG_LDS_ALLOC Per-wave LDS allocation.
H A Dgfx7_hwreg.rst50 HW_REG_HW_ID Id of wave, simd, compute unit, etc.
51 HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
52 HW_REG_LDS_ALLOC Per-wave LDS allocation.
H A Dgfx8_hwreg.rst50 HW_REG_HW_ID Id of wave, simd, compute unit, etc.
51 HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
52 HW_REG_LDS_ALLOC Per-wave LDS allocation.
H A Dgfx9_hwreg.rst50 HW_REG_HW_ID Id of wave, simd, compute unit, etc.
51 HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
52 HW_REG_LDS_ALLOC Per-wave LDS allocation.
H A Dgfx10_hwreg.rst50 HW_REG_HW_ID Id of wave, simd, compute unit, etc.
51 HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
52 HW_REG_LDS_ALLOC Per-wave LDS allocation.
/netbsd-src/games/warp/
H A Dscore.c152 totalscore = smarts = cumsmarts = wave = 0; in score_init()
162 wave = atoi(spbuf+36); in score_init()
182 totalscore,smarts,cumsmarts,numents,numbases,wave); in score_init()
404 wave++; in wavescore()
406 wave, smarts, cumsmarts); in wavescore()
656 totalscore = cumsmarts = wave = 0; in score()
682 logname, totalscore, smarts, cumsmarts, numents, numbases, wave, in save_game()
H A Dwarp.doc7 succeeding wave, up to difficulty 99. You're not likely to get that far.
15 Each wave starts with one Enterprise and one Base, and continues until
18 wave, but you will be penalized for it. The game may be saved between waves.
84 q asks if you want to exit this wave (will not work
86 Q exit this game (not wave)
127 so that there is no place to bounce to, the Tholians win that wave.
130 points accumulated this wave, the Enterprise's energy and torpedoes, the
178 a wave, you also get bonus points for saving stars, saving the Enterprise
183 done with a wave, but it won't quit, there may be homing torpedoes that you
H A Dwarp.c333 numents, numbases, wave, in main()
H A Dwarp.h406 EXT int wave; variable
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_gfx_v6_0.c2991 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
2994 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
3002 uint32_t wave, uint32_t thread, in wave_read_regs() argument
3006 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
3016 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v6_0_read_wave_data() argument
3020 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v6_0_read_wave_data()
3021 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v6_0_read_wave_data()
3022 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v6_0_read_wave_data()
3023 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v6_0_read_wave_data()
3024 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v6_0_read_wave_data()
[all …]
H A Damdgpu_gfx.h198 uint32_t wave, uint32_t *dst, int *no_fields);
200 uint32_t wave, uint32_t thread, uint32_t start,
203 uint32_t wave, uint32_t start, uint32_t size,
H A Damdgpu_debugfs.c708 uint32_t offset, se, sh, cu, wave, simd, data[32]; in amdgpu_debugfs_wave_read() local
718 wave = (*pos & GENMASK_ULL(36, 31)) >> 31; in amdgpu_debugfs_wave_read()
731 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); in amdgpu_debugfs_wave_read()
787 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; in amdgpu_debugfs_gpr_read() local
797 wave = (*pos & GENMASK_ULL(43, 36)) >> 36; in amdgpu_debugfs_gpr_read()
816 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
819 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
H A Damdgpu_gfx_v7_0.c4149 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
4152 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
4160 uint32_t wave, uint32_t thread, in wave_read_regs() argument
4164 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
4174 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v7_0_read_wave_data() argument
4178 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v7_0_read_wave_data()
4179 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v7_0_read_wave_data()
4180 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v7_0_read_wave_data()
4181 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v7_0_read_wave_data()
4182 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v7_0_read_wave_data()
[all …]
H A Damdgpu_gfx_v10_0.c1110 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) in wave_read_ind() argument
1113 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
1118 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, in wave_read_regs() argument
1123 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
1131 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint… in gfx_v10_0_read_wave_data() argument
1140 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); in gfx_v10_0_read_wave_data()
1141 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); in gfx_v10_0_read_wave_data()
1142 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); in gfx_v10_0_read_wave_data()
1143 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); in gfx_v10_0_read_wave_data()
1144 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); in gfx_v10_0_read_wave_data()
[all …]
H A Damdgpu_gfx_v8_0.c5213 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
5216 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
5224 uint32_t wave, uint32_t thread, in wave_read_regs() argument
5228 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
5238 static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v8_0_read_wave_data() argument
5242 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v8_0_read_wave_data()
5243 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v8_0_read_wave_data()
5244 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v8_0_read_wave_data()
5245 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v8_0_read_wave_data()
5246 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v8_0_read_wave_data()
[all …]
H A Damdgpu_gfx_v9_0.c1924 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
1927 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
1935 uint32_t wave, uint32_t thread, in wave_read_regs() argument
1939 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
1949 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v9_0_read_wave_data() argument
1953 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_0_read_wave_data()
1954 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_0_read_wave_data()
1955 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_0_read_wave_data()
1956 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_0_read_wave_data()
1957 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_0_read_wave_data()
[all …]
/netbsd-src/external/bsd/file/dist/magic/magdir/
H A Driff9 # https://www.iana.org/assignments/wave-avi-codec-registry/wave-avi-codec-registry.xml
13 0 name riff-wave
132 >>>8 use riff-wave
229 # WAVE/AVI codec registry: https://www.iana.org/assignments/wave-avi-codec-registry/wave-avi-codec-…
285 #!:mime audio/vnd.wave
289 !:ext wav/wave
362 # https://www.iana.org/assignments/wave-avi-codec-registry/wave-avi-codec-registry.xml
822 >24 string wave\xF3\xAC\xD3\x11\x8C\xD1\x00\xC0\x4F\x8E\xDB\x8A \b, WAVE 64 audio
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/gcn/
H A Dgcn.opt71 -mstack-size=<number> Set the private segment size per wave-front, in bytes.
/netbsd-src/external/gpl3/gcc/dist/gcc/config/gcn/
H A Dgcn.opt69 -mstack-size=<number> Set the private segment size per wave-front, in bytes.
/netbsd-src/games/quiz/datfiles/
H A Dlatin23 fluctus (n.):wave{s}
/netbsd-src/external/gpl2/groff/dist/tmac/
H A Dhyphenex.us767 wave-guide
768 wave-let
769 wave-lets
/netbsd-src/sys/arch/luna68k/dev/xplx/
H A Dxplx.asm1518 ; output PAM wave = normal 5 + antinoise 1
1629 ; output PAM wave = 4
1722 ; output PAM wave = normal 5 + antinoise 1
1854 ; output PAM wave = 2
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td177 // FIXME: Should be mangled for wave size.
435 llvm_i1_ty, // wave release, usually set to 1
436 llvm_i1_ty], // wave done, set to 1 for the last ordered instruction
1484 // current wave. Otherwise, the result is undefined.
1491 // currently active threads of the current wave. Otherwise, the result is
/netbsd-src/sys/arch/hppa/dev/
H A Dcpudevs239 board HP800_L150044 0x5d8 800/L1500-44/rp5430 (Rhapsody wave 2 W+)
240 board HP800_L150036 0x5d9 800/L1500-36/rp5430 (Rhapsody wave 2 W+)
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIInstrFormats.td69 // on wave termination. It is necessary to distinguish from mayStore

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